Publications

Found 231 results
1998
D. Chang, Lee, T. - C., Cheng, K. - T., and Marek-Sadowska, M., Functional scan chain testing, in Design, Automation and Test in Europe, 1998., Proceedings, 1998, pp. 278 -283.
D. I. Cheng, Cheng, K. - T., Wang, D. C., and Marek-Sadowska, M., A hybrid methodology for switching activities estimation, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 17, pp. 357 -366, 1998.
C. - C. Lin, Marek-Sadowska, M., Cheng, K. - T., and Lee, T. - C., Test-point insertion: scan paths through functional logic, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 17, pp. 838 -851, 1998.
1999
A. Singh and Marek-Sadowska, M., Circuit clustering using graph coloring, in ISPD '99: Proceedings of the 1999 international symposium on Physical design, 1999, pp. 164–169.
S. - C. Chang, Van Ginneken, L. P. P. P., and Marek-Sadowska, M., Circuit optimization by rewiring, Computers, IEEE Transactions on, vol. 48, pp. 962 -970, 1999.
A. Vittal, Chen, L. H., Marek-Sadowska, M., Wang, K. - P., and Yang, S., Crosstalk in VLSI interconnections, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 18, pp. 1817 -1824, 1999.
T. Xiao and Marek-Sadowska, M., Crosstalk reduction by transistor sizing, in Design Automation Conference, 1999. Proceedings of the ASP-DAC '99. Asia and South Pacific, 1999, pp. 137 -140 vol.1.
C. - C. Lin, Chen, K. - C., and Marek-Sadowska, M., Logic synthesis for engineering change, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 18, pp. 282 -292, 1999.
A. Vittal, Chen, L. H., Marek-Sadowska, M., Wang, K. - P., and Yang, S., Modeling crosstalk in resistive VLSI interconnections, in VLSI Design, 1999. Proceedings. Twelfth International Conference On, 1999, pp. 470 -475.
D. Chang and Marek-Sadowska, M., Partitioning sequential circuits on dynamically reconfigurable FPGAs, Computers, IEEE Transactions on, vol. 48, pp. 565 -578, 1999.
K. - H. Tsai, Tompson, R., Rajski, J., and Marek-Sadowska, M., STAR-ATPG: a high speed test pattern generator for large scan designs, in Test Conference, 1999. Proceedings. International, 1999, pp. 1021 -1030.
A. Mukherjee, Marek-Sadowska, M., and Long, S. I., Wave pipelining YADDs-a feasibility study, in Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999, 1999, pp. 559 -562.
A. Mukherjee, Sudhakar, R., Marek-Sadowska, M., and Long, S. I., Wave steering in YADDs: a novel non-iterative synthesis and layout technique, in Design Automation Conference, 1999. Proceedings. 36th, 1999, pp. 466 -471.
2000
L. H. Chen and Marek-Sadowska, M., Aggresors alignment for worst-case coupling noise, in ICCAD '00: Proceedings of the 2000 international conference on Computer-aided design, 2000, pp. 48–54.
L. H. Chen and Marek-Sadowska, M., Aggressor alignment for worst-case coupling noise, in ISPD '00: Proceedings of the 2000 international symposium on Physical design, 2000, pp. 48–54.
L. H. Chen, Marek-Sadowska, M., Divecha, R., and Singh, P., Capturing input switching dependency in crosstalk noise modeling, in ASIC/SOC Conference, 2000. Proceedings. 13th Annual IEEE International, 2000, pp. 330 -334.
T. Xiao and Marek-Sadowska, M., Efficient delay calculation in presence of crosstalk, in Quality Electronic Design, 2000. ISQED 2000. Proceedings. IEEE 2000 First International Symposium on, 2000, pp. 491 -497.
T. Xiao, Chang, C. - W., and Marek-Sadowska, M., Efficient static timing analysis in presence of crosstalk, in ASIC/SOC Conference, 2000. Proceedings. 13th Annual IEEE International, 2000, pp. 335 -339.
C. - W. Chang, Cheng, C. - K., Suaris, P., and Marek-Sadowska, M., Fast post-placement rewiring using easily detectable functional symmetries, in Design Automation Conference, 2000. Proceedings 2000. 37th, 2000, pp. 286 -289.
A. Singh, Macchiarulo, L., Mukherjee, A., and Marek-Sadowska, M., A novel high throughput reconfigurable FPGA architecture, in FPGA '00: Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays, 2000, pp. 22–29.
Y. - L. Wu, Fan, H., Marek-Sadowska, M., and Wong, C. K., OBDD minimization based on two-level representation of Boolean functions, Computers, IEEE Transactions on, vol. 49, pp. 1371 -1379, 2000.
K. - H. Tsai, Rajski, J., and Marek-Sadowska, M., Star test: the theory and its applications, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 19, pp. 1052 -1064, 2000.
L. Macchiarulo, Shu, S. - M., and Marek-Sadowska, M., Wave steered FSMs, in Design, Automation and Test in Europe Conference and Exhibition 2000. Proceedings, 2000, pp. 270 -276.
L. Macchiarulo and Marek-Sadowska, M., Wave-steering one-hot encoded FSMs, in DAC '00: Proceedings of the 37th Annual Design Automation Conference, 2000, pp. 357–360.
T. Xiao and Marek-Sadowska, M., Worst delay estimation in crosstalk aware static timing analysis, in Computer Design, 2000. Proceedings. 2000 International Conference on, 2000, pp. 115 -120.

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