# Publications

“An accurate and efficient delay model for CMOS gates in switch-level timing analysis”, in Circuits and Systems, 1990., IEEE International Symposium on, 1990, pp. 856 -860 vol.2.

, “Logic synthesis for engineering change”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 18, pp. 282 -292, 1999.

, “Scan paths through functional logic”, in Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996, 1996, pp. 487 -490.

, “Cost-free scan: a low-overhead scan path design”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 17, pp. 852 -861, 1998.

, “On designing universal logic blocks and their application to FPGA design”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 16, pp. 519 -527, 1997.

, “Universal Logic Gate For Fpga Design”, in Computer-Aided Design, 1994., IEEE/ACM International Conference on, 1994, pp. 164 -168.

, “Stepwise equivalent conductance circuit simulation technique”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 12, pp. 672 -683, 1993.

, “A fast and efficient algorithm for determining fanout trees in large networks”, in Design Automation. EDAC., Proceedings of the European Conference on, 1991, pp. 539 -544.

, “Cost-free scan: a low-overhead scan path design methodology”, in Computer-Aided Design, 1995. ICCAD-95. Digest of Technical Papers., 1995 IEEE/ACM International Conference on, 1995, pp. 528 -533.

, “Performance study of VeSFET-based, high-density regular circuits”, in ISPD '10: Proceedings of the 19th international symposium on Physical design, 2010, pp. 161–168.

, “Test point insertion: scan paths through combinational logic”, in Design Automation Conference Proceedings 1996, 33rd, 1996, pp. 268 -273.

, “Is there always performance overhead for regular fabric?”, in Computer Design, 2008. ICCD 2008. IEEE International Conference on, 2008, pp. 557 -562.

, “Delay and area optimization in standard-cell design”, in Design Automation Conference, 1990. Proceedings., 27th ACM/IEEE, 1990, pp. 349 -352.

, “Test-point insertion: scan paths through functional logic”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 17, pp. 838 -851, 1998.

, “Sequential permissible functions and their application to circuit optimization”, in European Design and Test Conference, 1996. ED TC 96. Proceedings, 1996, pp. 334 -339.

, “A New Accurate and Efficient Timing Simulator”, in VLSI Design, 1992. Proceedings., The Fifth International Conference on, 1992, pp. 281 -286.

, “Layout Generator for Transistor-Level High-Density Regular Circuits”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 29, pp. 197 -210, 2010.

, “Wire length prediction-based technology mapping and fanout optimization”, in ISPD '05: Proceedings of the 2005 international symposium on Physical design, 2005, pp. 145–151.

, “A congestion-driven placement framework with local congestion prediction”, in GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI, 2005, pp. 488–493.

, “Pre-layout wire length and congestion estimation”, in Design Automation Conference, 2004. Proceedings. 41st, 2004, pp. 582 -587.

, “Wire length prediction in constraint driven placement”, in SLIP '03: Proceedings of the 2003 international workshop on System-level interconnect prediction, 2003, pp. 99–105.

, “A study of netlist structure and placement efficiency”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, pp. 762 - 772, 2005.

, “Semi-individual wire-length prediction with application to logic synthesis”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 25, pp. 611 - 624, 2006.

, “Pre-layout physical connectivity prediction with application in clustering-based placement”, in Computer Design: VLSI in Computers and Processors, 2005. ICCD 2005. Proceedings. 2005 IEEE International Conference on, 2005, pp. 31 - 37.

, “Individual wire-length prediction with application to timing-driven placement”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 12, pp. 1004 -1014, 2004.

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