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Aikyo, T
Aitken, J
Anderson, B
Brewer, F
Chai, D
Chang, Ya-Ting
Chang, Shih-Chieh
Chang, Chih-Wei
Chang, D
Chen, L H
Chen, Fen
Chen, B
Chen, Sao-Jie
Chen, Z
Chen, Kuang-Chien
Cheng, Kwang-Ting
Cheng, David I
Cheng, Chung-Kuan
Divecha, R
Dutta, R
Fan, Hongbing
Feng, K D
Funabiki, N
Gatlin, D
Grygiel, S
Ha, H
Hellebrand, S
Henson, W K
Hsiao, Ming-Fu
Hu, Bo
Jiang, Hailin
Jiang, Yi-Min
Jozwiak, L
Kane, T
Kasprowicz, D
Kinser, E
Kondratyev, A
Kontra, R
Kozhaya, J
Krstic, A
Kuh, E S
Kumar, M
Kuo, Yu-Min
Kuzmicz, W
Lee, Bill
Lee, Tien-Chien
Li, Di-an
Li, X
Li, Jeong-Tyng
Lin, Chih-Chang
Lin, Yi-Wei
Lin, Shen
Liu, Qinghua
Long, S I
Luba, T
Macchiarulo, Luca
Maire, F
Makedon, Fillia
Malvi, R
Maly, Wojciech
Maly, Wojciech
Marek-Sadowska, Malgorzata
Marek-Sadowska, M
Matheron, C
Mehta, Vishal
Merek-Sadowska, Malgorzata
Mittl, S
Mocuta, D
Modi, Nilesh
Mukherjee, Arindam
Nandakumar, V S
Nassif, S R
Newmark, D
Nowicka, M
Parthasarathy, G
Parthasarathy, Ganapathy
Pedram, M
Perkowski, M
Pfitzner, A
Pikus, Fedor G
Qiu, Xiang
Rajski, Janusz
Ran, Yajun
Rieger, Michael L
Sarrafzadeh, M
Shen, N
Shinosky, M
Shu, Shih-Min
Singh, P
Singh, Vivek K
Singh, Amit
Singh, N
Su, Yu-Shih
Suaris, P
Sudhakar, R
Swift, A
Tarng, Tom Tsan-Kuo
Todri, Aida
Tompson, R
Torres, Andres
Tsai, Kun-Han
Tsai, Chien-Chung
Tsai, Chung-Kuan
Tseng, Kenneth
Tsukiyama, Shuji
Van Ginneken, L P P P
Vittal, Ashok
Wang, Deborah C
Wang, Da-Chung
Wang, Kai-Ping
Wang, Zhi
Wang, Yun
Wang, Yanfeng
Wang, Kai
Wang, Zhiyuan
Watanabe, Yosinori
Weng, Shih-Hung
Wong, C K
Woo, Nam-Sung
Wu, Yu-Liang
Wuu, Jen-Yi
Xiao, Tong
Yang, Sherry
Yeh, Chao-Yang
Zeng, Yue
Zhan, Yaping
Zhang, Jin S
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Conference Paper
Journal Article
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Year
any
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Keyword
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0.25 micron
0.5 micron
0.5 mum
130 nm
180 nm
2-D FPGAs
2-layer channel-routing problem
2.5 V
2D array
2D FPGA
2D FPGA routing
2D interval packing problem
3-D geometry transistor
3D architectural blocks
3D design space exploration
3D hybrid architecture
3D integration
3D junctionless VeSFET
3D multicore architectures
3D multicore processor
3D network-on-chip architecture
500 MHz
625 MHz
65 nm
715 MHz
90 nm
abutment
accuracy
Actel 2
active area
add-a-wire-and-remove-a-wire operation
adders
addition
advanced VLSI circuits
aggressor
aggressor alignment
algebraic factorization
algorithm
algorithms
alternative function
alternative wire
alternative wire identification
alternative wires
analysis tool
analytic placement
AND gates
AND/XOR canonical networks
AND/XOR representations
annealing refinement stage
application specific integrated circuits
application-specified integrated circuits
approximation accuracy
arbitrary fixed switch box topology
architectural level routing
architecture resources
area improvement
area optimization
area overhead
area-optimization heuristic
arithmetic functions
array size
array type architectures
array-type FPGA
ASIC
ASIC design
ASICs
assymetrical bidirectional currents
ATPG
ATPG guided logic optimization
ATPG-based logic synthesis
automatic place
automatic synthesis
automatic test pattern generation
automatic testing
automatic-test-pattern-generated sets
back-mapping
back-mapping process
basic arithmetic operations
basic logic block
BDD
BDD-based techniques
BDD-type structures
BDDs
bin-packing heuristic
binary decision diagram
binary decision diagrams
block-based statistical static timing analysis
Boolean algebra
Boolean cover
Boolean equations
Boolean formulation
Boolean function
Boolean function classes
Boolean functions
Boolean functions classification
Boolean logic
Boolean logic optimization
Boolean matching
Boolean network
Boolean network functional symmetries
Boolean networks
boolean optimization
Boolean optimization method
Boolean satisfiability
boundary scan testing
bounding box placers
BSIM3v3 model
buffer area
buffer area minimisation
buffer circuits
buffer delay change
buffer delay model
buffer insertion
buffer resizing
buffer width
buffered clock trees
built-in self test
built-in-self-test
C-SBGT algorithm
cache block
CAD
candidate wires
canonical forms
capacitance
capacitive coupling-induced crosstalk noise
capacitive coupling-induced delay
capacitive couplings
capacitive loading
capacitively coupled lines
capacitor switching
carrier velocity saturation
CD threshold
cell based design
cell class
cell interconnect layouts
cell layout-performance relationships
cell level routing
cell library
cell power noise estimation
cell-level interconnect pattern
cellular arrays
channel density
chip
chip manufacturability
chip performance
chip performance optimization
circuit analysis computing
circuit blocks
circuit CAD
circuit clocking frequency
circuit clustering
circuit complexity
circuit component delays
circuit delay
circuit delays
circuit depth optimization
circuit design
circuit design methodology
circuit diagnosis
circuit elements
circuit functional property
circuit layout
circuit layout CAD
circuit mappability prediction
circuit model
circuit noise
circuit operation
circuit optimisation
circuit optimization
circuit parameters
circuit partitioning
circuit performance
circuit performance optimization
circuit placement algorithm
circuit reliability
circuit rewiring
circuit simulation
circuit sizes
circuit stability
circuit structures
circuit techniques
circuit testability
circuit testing
circuit timing
circuit timing information
circuit timing property
circuit timing-information
clock buffers
clock gating
clock jitter
clock mesh distribution networks
clock nets
clock network
clock network optimization
clock network sizing
clock path delay
clock period constraints
clock routing
clock skew
clock skew optimization
clock topologies
clock topology
clocking
clocking components
clocks
closed-form crosstalk delay metrics
closed-form crosstalk noise metrics
closed-form estimation formulas
closed-form formulas
clustering
clustering netlist
clustering-based placement
CMOS circuits
CMOS digital integrated circuits
CMOS gates
CMOS integrated circuits
CMOS logic circuits
CMOS static cells
CMOS technology
CMOS VLSI circuits
coarse mesh
cofactor pair compatibility
combinational circuit
combinational circuits
combinational logic
combinational logic functions
combinational logic restructuring
combinational logic restructuring technique
combinatorial circuits
complementary metal-oxide-semiconductor-based homogeneous 3D NoC
completely specified functions
complex logic transformations
complexity
computability
computation-intensive combinational circuits
computational complexity
conductance circuit simulation technique
congestion minimization techniques
connection flexibility
constant bounded mapping ratios
constant insertion
constant-delay model
constrained region graph
constraint-driven routing
control sequence
controllability
conventional clock tree synthesis
convergent
copper contact
correlation methods
cost function optimization
cost functions
cost-free scan
coupled circuits
coupled clock networks
coupled noise
coupled noise integral
coupled noise reduction
coupling capacitance
coupling direction
coupling effects
coupling jitter
coupling location
cover pattern processing
critical net
crossing distribution problem
crosstalk
crosstalk amplitude
crosstalk aware static timing analysis
crosstalk aware two-pin net router
crosstalk computation
crosstalk coupling
crosstalk delay effects
crosstalk effect
crosstalk induced critical paths identification
crosstalk induced delay
crosstalk minimization
crosstalk modeling
Crosstalk noise
crosstalk noise analysis
crosstalk noise analysis method
crosstalk noise dependency
crosstalk noise modeling
crosstalk pulse width
crosstalk reduction
crosstalk violations removal
crosstalk-induced delay
cube diagram bundles
current densities
current density
custom designed transistor level macros
data structure
datapath circuit
datapath circuits
datapath combinational circuits
dc current densities
DC voltage-transfer characteristics
decap
decap area
decap configuration
decap distribution
decap padding
decaying
decaying effect
decoupling capacitance
decoupling capacitance insertion
decoupling capacitor effectiveness
deep sub-micron technologies
deep submicron chip design
deep submicron digital circuits
deep submicron integrated circuit design
deep submicron technologies
deep submicron technology
deep-submicron circuits
delay
delay analysis
delay budgeting
delay calculation method
delay circuits
delay constrained power optimization
delay defect size
delay equalization
delay estimation
delay expressions
delay fault diagnosis
delay fault identification
delay fault testing
delay model
delay models
delay optimization
delay overhead
delay testing
delay upper bounds
delay variation
delay window propagation
delay-defect diagnosis
delay-defect-size estimations
delay-fault diagnosis
delays
design complexity
design for manufacture
design for testability
design mappability estimation
design methodology
design reliability
design specifications
design timing
design timing failures
design-for-reliability tools
design-for-testability
design-timing failures
detailed routing
deterministic algorithms
deterministic patterns
deterministic routing
DFT
DFT overhead
diagnosis algorithm
diagnostic resolution
diagnostic test patterns
dielectric breakdown
diffusion contacts
digital arithmetic
digital circuit crosstalk
digital circuit optimization
digital circuits
digital integrated circuits
digital MOS circuits
digital VLSI circuit design
direct mapping
directed acyclic graph
directed graphs
discrete gate resizing
discrete-size cell library
distributed parameter networks
distributed RC coupling network
distributed RC coupling trees
divide and conquer methods
divide-and-conquer
division
doglegs
don't cares
Donath method
double-gate transistor-array-based layout
Dragon routability-driven placer
DRAM chips
driver circuits
driver size
driving capabilities
DWP
dynamic noise margins
dynamic power dissipation
dynamic transient current
dynamically reconfigurable FPGAs
earthing
ECL encoder chip
ECO-Map
edge separability
efficiency
efficient algorithm
efficient ordering heuristic
electric noise measurement
electrical constraints
electrical property
electromigration
electromigration constraints
electromigration phenomena
electronic devices
electronic engineering computing
electrostatic discharge
element proximity
empirical measure
energy consumption
engineering change
engineering change orders
engineering changes
epitaxial source-drain
equivalence classes
equivalent circuits
equivalent resistances
error correction
estimate-then-eliminate strategies
estimation theory
estimation-less placement
evaluation machine
expansion-based placer
exponent computation
external don't cares
extra variable
failing pattern analysis
failure analysis
failure analyzer
failure log processing
failure logs
failure mechanisms
fan-out optimization
fanout trees
far-end coupling
fast design convergence
fast design mappability estimation
fast physical verification tool
fast placer implementation
fast placer implementation framework
fast postplacement optimization
fast timing verification
fast turn-around times
fault clustering
fault clustering analysis
fault coverage
fault detection
fault diagnosis
fault location
fault multiplicity
fault simulation
FF reduction algorithm
field effect integrated circuits
field effect transistor circuits
field effect transistors
field programmable gate array
field programmable gate arrays
fine grain 3D integrated regular microprocessor blocks
fine granularity clustering-based placement
fine-granularity clustering algorithm
FinFET
finite state machines
finite-state machines
first-order Taylor expansion
fixed metal masks
fixed point arithmetic
fixed polarity
Fixed Polarity Reed-Muller form
fixed polarity Reed-Muller forms
fixed-point addition
fixed-polarity AND/XOR canonical networks minimisation
flip-flop
flip-flop minimization
flip-flops
flipflop minimization
floorplanning
force directed placement
force directed scheduling
formal verification
four-variable functions
FPGA
FPGA design
FPGA placement
FPGA routing
FPGA routing architecture
FPGA structures
FPGA-based design
FPI
FPI framework
free-scan flip-flops
FSM
FSM decomposition theory
full-scan design
function representation
functional correlation analysis
functional equivalence
functional flexibility
functional irredundant path sensitization criteria
functional logic
functional scan chain testing
functional scan paths
functional symmetries
functional symmetry
functional symmetry based rewiring
GA approach
gain control
Gain-based technology mapping
gate arrays
gate delay
gate delay calculation
gate delays
gate sizing
gate-level Boolean networks
gate-level model
gate-level timing calculation
gate-sizing algorithm
gate-sizing method
gate-to-drain capacitances
gate-to-source capacitances
gated blocks
general cell layouts
general skew constraints
general-purpose fabric
generalised Reed-Muller form
Generalized Reed-Muller
generalized Reed-Muller forms
genetic algorithms
global nets
global placement
global power supply noise
global route mapping
global routing
global routing channel density
global routing technique
global to detailed routing mapping
graph based analysis
graph domain
graph models
graph partitioning
graph theory
greedy 2-D router
greedy channel router
greedy coupling heuristics
greedy routing architectures
grid segments
grid sizing
ground bounce
ground bounce control
ground grid networks
ground mesh sizing problem
ground node potentials
ground noise
group compatibility
H tree
H-tree
hardware cost
heterogeneous 3D chip
heuristic
heuristic algorithm
heuristic approach
heuristic methodology
heuristic switch-level model
hierarchical FPGAs
hierarchical technique
hierarchical test set structure
high diagnostic resolution
high fault coverage
high level synthesis
high performance arithmetic circuits
high speed test pattern generator
high throughput circuits
high-density regular circuits
high-density transistor arrays
high-speed integrated circuits
high-throughput circuit generation
highly periodic layout
hold logic
hold logic design
hold time defect diagnosis
hold time fault diagnosis
hold time violations
horizontal connections
hot carriers
hot-carrier effect
hotspot detection tool
hotspot pattern identification
HSPICE simulation
HSPICE simulations
hybrid methodology
I/O pads
IC design
IC layout
IC manufacturability
IC testing
idle blocks
implicit algorithm
implicit white space allocation
improved performance
in-place optimization
incompletely specified functions
incompletely specified multiple output functions
incremental cell movement scheme
incremental circuit restructuring
incremental logic restructuring
individual wire length prediction
industrial applications
industrial designs
infrared voltage drop effects
inner loops
input negation
input permutation
input switching conditions
input switching dependency capture
input vectors
insulated gate field effect transistors
insulators
integer linear programming
integer programming
integrated circuit
integrated circuit design
integrated circuit fabrication
integrated circuit interconnections
integrated circuit layout
integrated circuit manufacture
integrated circuit manufacturing
integrated circuit measurement
integrated circuit modelling
integrated circuit noise
integrated circuit packaging
integrated circuit reliability
integrated circuit technology
integrated circuit testing
integrated circuits
integrated design flow
integrated logic circuits
integration
intellectual property blocks
inter clock crosstalk
inter-block connections
inter-clock crosstalk
intercell routing
intercell white space
interconnect coupling noise
interconnect delays
interconnect insensitive driver model
interconnect length prediction
interconnect prediction
interconnect resource-aware placement
interconnect structure
interconnect-related failure modes
interconnected IP cores
interconnection
interconnection complexity
interconnections
interconnects
interference suppression
internal nodes
intra-block connections
intracell routing
intrinsic delay
IR drop
IR drop noise
IR drop waveforms
ISCAS
iteration
iterative method
iterative methods
iterative updating
jitter
jitter characteristics
large CMOS designs
large networks
large scale integration
large scan designs
large-scale mesh
large-scale network
latch count minimization
latches
latency
latency penalties
layout
layout aspect ratio
layout effects
layout friendly structures
layout friendly synthesized structures
layout generator
layout object printability
layout style
layout techniques
layout-driven hot-carrier degradation
layout-driven synthesis
leakage currents
leakage power
leakage power reduction
leakage power saving
learning (artificial intelligence)
level-induced jitter
linear circuit elements
linear equations
linear model
linear network analysis
linear program sequence
linear programming
linear programming approach
linear programming-based technique
linear time complexity
linear time-varying driver model
linear-region model
linear-time algorithm
linearized pseudo-symmetric binary decision diagram
literal minimization
lithographic hotspot detection
lithography
local nets
local power supply voltage
local truncation error
locally optimal switch box routing
logic arrays
logic assignments
logic CAD
logic circuits
logic contraction
logic design
logic effort
logic function
logic gates
logic minimization
logic minimization techniques
logic optimization
logic optimization techniques
logic partitioning
logic perturbation
logic representation
logic restructuring
logic restructuring techniques
logic simulation
logic stage
logic synthesis
logic synthesis algorithms
logic testing
logic verification
long wires
long-term reliability
longest delay
look-up tables
lookup-table-type
low complexity
low energy network-on-chip fabric
low granularity pipelining
low-cost BIST scheme
low-overhead scan design methodology
low-overhead scan path design
low-power buffered clock tree design
low-power electronics
lower bound complexity
lower levels
lower-bound time complexity
LTV model
M1-M2 via mask
machine learning
mandatory assignments
manufacturing defects
manufacturing process variations
mappability
mapping
mapping properties
mapping ratio
mapping solutions
mask cost
masks
maximum IR-drop constraints
MCNC
MCNC benchmark
MCNC benchmarks
MCNC circuits
memory array macros
mesh topology
metal gate
metal layers
metal masks
metric of dynamic binateness
microprocessor
microprocessor chips
middle-of-line PC-to-CA dielectric reliability
middle-of-line poly gate-to-diffusion contact reliability issues
min-max delay model
minimisation
minimisation of switching nets
minimization algorithms
minimize
minimizing inter clock coupling jitter
minimum area sequential budgeting
minimum number of blocks
minmax delay model
modeling graph
modern chip designs
MOL PC-CA shorts
MOL PC-to-CA dielectric reliability
monolithic integrated circuits
Monte Carlo methods
MOS integrated circuits
MOS transistors
MOSFET
multi-level combinational circuits
multi-pin net lists
multicore processor
multicore processors
multicore system
multicore systems
multigrid-based technique
multilevel Boolean network optimizer
multilevel combinational networks
multilevel expansion-based VLSI placement
multilevel fixed point addition
multilevel logic synthesis
multilevel logic synthesis method
multilevel networks
multipin net
multiple candidate signals
multiple clock tree routing
multiple fault diagnosis
multiple gating schedules
multiple power gating
multiple-error diagnosis
multiple-fault diagnosis
multiple-valued decomposers
multiple-valued relations
multiple-valued relations decomposition
multiplexer
multiplication
multipliers
multiplying circuits
multiprocessing systems
multiterminal networks
multivalued logic
multivalued logic circuits
mutual contraction
mutually capacitively coupled signals
n-bit adder
n-detection
n-detection test
nanometer technology
nanotechnology
natural representations
near-driver coupling location
near-end coupling direction
near-receiver coupling
net absorption
net absorption algorithm
net ordering
net partitioning
net range
net slack
net weighting delays
netlist
netlist cluster
netlist structure
nets intersection
network optimization
network parameter
network routing
network synthesis
network topology
network-on-chip
NoC
NoC communication fabric
noise
noise delay faults
noise elimination
noise estimation
noise fault
noise faults
noise signals
noise sources
noise waveform
noise waveform width
noise-constrained layout synthesis
noise-on-signal propagation
noniterative layout technique
noniterative synthesis technique
nonlinear programming
nonlinear programming problem
nonlinear res
