Publications

Found 231 results
Conference Paper
Y. - L. Wu, Chang, D., Marek-Sadowska, M., and Tsukiyama, S., “Not necessarily more switches more routability [sic.]”, in Design Automation Conference 1997. Proceedings of the ASP-DAC '97. Asia and South Pacific, 1997, pp. 579 -584.
A. Singh, Macchiarulo, L., Mukherjee, A., and Marek-Sadowska, M., “A novel high throughput reconfigurable FPGA architecture”, in FPGA '00: Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays, 2000, pp. 22–29.
M. Marek-Sadowska, “On old and new routing problems”, in ISPD '11: Proceedings of the 2011 international symposium on Physical design, 2011, pp. 13–20.
Li, Di-an, Marek-Sadowska, M., and Lee, B., “On-chip em-sensitive interconnect structures”, in SLIP '10: Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction, 2010, pp. 43–50.
K. Wang and Marek-Sadowska, M., “On-chip power supply network optimization using multigrid-based technique”, in Design Automation Conference, 2003. Proceedings, 2003, pp. 113 - 118.
W. Maly, Yi-Wei Lin, and Marek-Sadowska, M., “OPC-Free and Minimally Irregular IC Design Style”, in Design Automation Conference, 2007. DAC '07. 44th ACM/IEEE, 2007, pp. 954 -957.
Y. - L. Wu and Marek-Sadowska, M., “Orthogonal Greedy Coupling - A New Optimization Approach to 2-D FPGA Routing”, in Design Automation, 1995. DAC '95. 32nd Conference on, 1995, pp. 568 -573.
Yi-Wei Lin, Marek-Sadowska, M., and Maly, W., “Performance study of VeSFET-based, high-density regular circuits”, in ISPD '10: Proceedings of the 19th international symposium on Physical design, 2010, pp. 161–168.
S. - C. Chang and Marek-Sadowska, M., “Perturb And Simplify: Multi-level Boolean Network Optimizer”, in Computer-Aided Design, 1994., IEEE/ACM International Conference on, 1994, pp. 2 -5.
S. - C. Chang and Marek-Sadowska, M., “Perturb and simplify: optimizing circuits with external don't cares”, in European Design and Test Conference, 1996. ED TC 96. Proceedings, 1996, pp. 402 -406.
M. Marek-Sadowska and Lin, S., “Pin assignment for improved performance in standard cell design”, in Computer Design: VLSI in Computers and Processors, 1990. ICCD '90. Proceedings., 1990 IEEE International Conference on, 1990, pp. 339 -342.
Y. - M. Jiang, Krstic, A., Cheng, K. - T., and Marek-Sadowska, M., “Post-layout Logic Restructuring For Performance Optimization”, in Design Automation Conference, 1997. Proceedings of the 34th, 1997, pp. 662 -665.
K. Wang and Marek-Sadowska, M., “Potential slack budgeting with clock skew optimization”, in Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. IEEE International Conference on, 2004, pp. 265 - 271.
A. Vittal and Marek-Sadowska, M., “Power Distribution Topology Design”, in Design Automation, 1995. DAC '95. 32nd Conference on, 1995, pp. 503 -507.
H. Jiang and Marek-Sadowska, M., “Power gating scheduling for power/ground noise reduction”, in Design Automation Conference, 2008. DAC 2008. 45th ACM/IEEE, 2008, pp. 980 -985.
A. Vittal and Marek-Sadowska, M., “Power Optimal Buffered Clock Tree Design”, in Design Automation, 1995. DAC '95. 32nd Conference on, 1995, pp. 497 -502.
A. Todri, Marek-Sadowska, M., and Kozhaya, J., “Power supply noise aware workload assignment for multi-core systems”, in Computer-Aided Design, 2008. ICCAD 2008. IEEE/ACM International Conference on, 2008, pp. 330 -337.
H. Jiang and Marek-Sadowska, M., “Power-Gating Aware Floorplanning”, in Quality Electronic Design, 2007. ISQED '07. 8th International Symposium on, 2007, pp. 853 -860.
K. Wang and Marek-Sadowska, M., “Power/ground mesh area optimization using multigrid-based technique [IC design]”, in Design, Automation and Test in Europe Conference and Exhibition, 2003, 2003, pp. 850 - 855.
H. Jiang and Marek-Sadowska, M., “Power/Ground Supply Network Optimization for Power-Gating”, in Computer Design, 2006. ICCD 2006. International Conference on, 2006, pp. 332 -337.
Q. Liu and Marek-Sadowska, M., “Pre-layout physical connectivity prediction with application in clustering-based placement”, in Computer Design: VLSI in Computers and Processors, 2005. ICCD 2005. Proceedings. 2005 IEEE International Conference on, 2005, pp. 31 - 37.
Q. Liu and Marek-Sadowska, M., “Pre-layout wire length and congestion estimation”, in Design Automation Conference, 2004. Proceedings. 41st, 2004, pp. 582 -587.
J. - Y. Wuu, Pikus, F. G., Torres, A., and Marek-Sadowska, M., “Rapid layout pattern classification”, in Design Automation Conference (ASP-DAC), 2011 16th Asia and South Pacific, 2011, pp. 781 -786.
Y. - L. Wu and Marek-Sadowska, M., “Routing on regular segmented 2-D FPGAs”, in Design Automation Conference, 1995. Proceedings of the ASP-DAC '95/CHDL '95/VLSI '95., IFIP International Conference on Hardware Description Languages; IFIP International Conference on Very Large Scale Integration., Asian and South Pacific, 1995, pp. 329 -334.
K. - H. Tsai, Rajski, J., and Marek-Sadowska, M., “Scan encoded test pattern generation for BIST”, in Test Conference, 1997. Proceedings., International, 1997, pp. 548 -556.

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