Publications

Found 231 results
Conference Paper
D. I. Cheng, Marek-Sadowska, M., and Cheng, K. - T., Speeding up power estimation by topological analysis, in Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995, 1995, pp. 623 -626.
C. - Y. Yeh and Marek-Sadowska, M., Skew-programmable clock design for FPGA and skew-aware placement, in FPGA '05: Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays, 2005, pp. 33–40.
A. Mukherjee, Wang, K., Chen, L. H., and Marek-Sadowska, M., Sizing power/ground meshes for clocking and computing circuit components, in Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings, 2002, pp. 176 -183.
C. - W. Chang and Marek-Sadowska, M., Single-pass redundancy-addition-and-removal, in Computer Aided Design, 2001. ICCAD 2001. IEEE/ACM International Conference on, 2001, pp. 606 -609.
C. - C. Lin, Chen, K. - C., Marek-Sadowska, M., and Lee, T. - C., Sequential permissible functions and their application to circuit optimization, in European Design and Test Conference, 1996. ED TC 96. Proceedings, 1996, pp. 334 -339.
C. - C. Lin, Marek-Sadowska, M., Cheng, K. - T., and Lee, T. - C., Scan paths through functional logic, in Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996, 1996, pp. 487 -490.
K. - H. Tsai, Rajski, J., and Marek-Sadowska, M., Scan encoded test pattern generation for BIST, in Test Conference, 1997. Proceedings., International, 1997, pp. 548 -556.
Y. - L. Wu and Marek-Sadowska, M., Routing on regular segmented 2-D FPGAs, in Design Automation Conference, 1995. Proceedings of the ASP-DAC '95/CHDL '95/VLSI '95., IFIP International Conference on Hardware Description Languages; IFIP International Conference on Very Large Scale Integration., Asian and South Pacific, 1995, pp. 329 -334.
J. - Y. Wuu, Pikus, F. G., Torres, A., and Marek-Sadowska, M., Rapid layout pattern classification, in Design Automation Conference (ASP-DAC), 2011 16th Asia and South Pacific, 2011, pp. 781 -786.
Q. Liu and Marek-Sadowska, M., Pre-layout wire length and congestion estimation, in Design Automation Conference, 2004. Proceedings. 41st, 2004, pp. 582 -587.
Q. Liu and Marek-Sadowska, M., Pre-layout physical connectivity prediction with application in clustering-based placement, in Computer Design: VLSI in Computers and Processors, 2005. ICCD 2005. Proceedings. 2005 IEEE International Conference on, 2005, pp. 31 - 37.
H. Jiang and Marek-Sadowska, M., Power/Ground Supply Network Optimization for Power-Gating, in Computer Design, 2006. ICCD 2006. International Conference on, 2006, pp. 332 -337.
K. Wang and Marek-Sadowska, M., Power/ground mesh area optimization using multigrid-based technique [IC design], in Design, Automation and Test in Europe Conference and Exhibition, 2003, 2003, pp. 850 - 855.
H. Jiang and Marek-Sadowska, M., Power-Gating Aware Floorplanning, in Quality Electronic Design, 2007. ISQED '07. 8th International Symposium on, 2007, pp. 853 -860.
A. Todri, Marek-Sadowska, M., and Kozhaya, J., Power supply noise aware workload assignment for multi-core systems, in Computer-Aided Design, 2008. ICCAD 2008. IEEE/ACM International Conference on, 2008, pp. 330 -337.
A. Vittal and Marek-Sadowska, M., Power Optimal Buffered Clock Tree Design, in Design Automation, 1995. DAC '95. 32nd Conference on, 1995, pp. 497 -502.
H. Jiang and Marek-Sadowska, M., Power gating scheduling for power/ground noise reduction, in Design Automation Conference, 2008. DAC 2008. 45th ACM/IEEE, 2008, pp. 980 -985.
A. Vittal and Marek-Sadowska, M., Power Distribution Topology Design, in Design Automation, 1995. DAC '95. 32nd Conference on, 1995, pp. 503 -507.
K. Wang and Marek-Sadowska, M., Potential slack budgeting with clock skew optimization, in Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. IEEE International Conference on, 2004, pp. 265 - 271.
Y. - M. Jiang, Krstic, A., Cheng, K. - T., and Marek-Sadowska, M., Post-layout Logic Restructuring For Performance Optimization, in Design Automation Conference, 1997. Proceedings of the 34th, 1997, pp. 662 -665.
M. Marek-Sadowska and Lin, S., Pin assignment for improved performance in standard cell design, in Computer Design: VLSI in Computers and Processors, 1990. ICCD '90. Proceedings., 1990 IEEE International Conference on, 1990, pp. 339 -342.
S. - C. Chang and Marek-Sadowska, M., Perturb and simplify: optimizing circuits with external don't cares, in European Design and Test Conference, 1996. ED TC 96. Proceedings, 1996, pp. 402 -406.
S. - C. Chang and Marek-Sadowska, M., Perturb And Simplify: Multi-level Boolean Network Optimizer, in Computer-Aided Design, 1994., IEEE/ACM International Conference on, 1994, pp. 2 -5.
Yi-Wei Lin, Marek-Sadowska, M., and Maly, W., Performance study of VeSFET-based, high-density regular circuits, in ISPD '10: Proceedings of the 19th international symposium on Physical design, 2010, pp. 161–168.
Y. - L. Wu and Marek-Sadowska, M., Orthogonal Greedy Coupling - A New Optimization Approach to 2-D FPGA Routing, in Design Automation, 1995. DAC '95. 32nd Conference on, 1995, pp. 568 -573.

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