Publications

Found 231 results
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F. Chen, Mittl, S., Shinosky, M., Swift, A., Kontra, R., Anderson, B., Aitken, J., Wang, Y., Kinser, E., Kumar, M., Wang, Y., Kane, T., Feng, K. D., Henson, W. K., Mocuta, D., and Li, Di-an, Investigation of emerging middle-of-line poly gate-to-diffusion contact reliability issues, in Reliability Physics Symposium (IRPS), 2012 IEEE International, 2012, pp. 6A.4.1 -6A.4.9.
A. Singh, Parthasarathy, G., and Marek-Sadowska, M., Interconnect resource-aware placement for hierarchical FPGAs, in Computer Aided Design, 2001. ICCAD 2001. IEEE/ACM International Conference on, 2001, pp. 132 -136.
A. Singh, Mukherjee, A., and Marek-Sadowska, M., Interconnect pipelining in a throughput-intensive FPGA architecture, in FPGA '01: Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays, 2001, pp. 153–160.
C. - K. Tsai and Marek-Sadowska, M., An interconnect insensitive linear time-varying driver model for static timing analysis, in Quality of Electronic Design, 2005. ISQED 2005. Sixth International Symposium on, 2005, pp. 654 - 661.
G. Parthasarathy, Marek-Sadowska, M., Mukherjee, A., and Singh, A., Interconnect complexity-aware FPGA placement using Rent's rule, in SLIP '01: Proceedings of the 2001 international workshop on System-level interconnect prediction, 2001, pp. 115–121.
Y. Ran and Marek-Sadowska, M., An integrated design flow for a via-configurable gate array, in Computer Aided Design, 2004. ICCAD-2004. IEEE/ACM International Conference on, 2004, pp. 582 - 589.
C. - W. Chang, Hu, B., and Marek-Sadowska, M., In-place delay constrained power optimization using functional symmetries, in Design, Automation and Test in Europe, 2001. Conference and Exhibition 2001. Proceedings, 2001, pp. 377 -382.
Q. Liu, Hu, B., and Marek-Sadowska, M., Individual wire-length prediction with application to timing-driven placement, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 12, pp. 1004 -1014, 2004.
L. H. Chen and Marek-Sadowska, M., Incremental delay change due to crosstalk noise, in ISPD '02: Proceedings of the 2002 international symposium on Physical design, 2002, pp. 120–125.
V. Mehta, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., Improving the Resolution of Single-Delay-Fault Diagnosis, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 27, pp. 932 -945, 2008.
H
D. I. Cheng, Cheng, K. - T., Wang, D. C., and Marek-Sadowska, M., A hybrid methodology for switching activities estimation, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 17, pp. 357 -366, 1998.
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Y. - L. Wu and Marek-Sadowska, M., Graph based analysis of FPGA routing, in Design Automation Conference, 1993, with EURO-VHDL '93. Proceedings EURO-DAC '93. European, 1993, pp. 104 -109.
Y. - L. Wu, Tsukiyama, S., and Marek-Sadowska, M., Graph based analysis of 2-D FPGA routing, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 15, pp. 33 -44, 1996.
N. Funabiki, Singh, A., Mukherjee, A., and Marek-Sadowska, M., A global routing technique for wave-steered design methodology, in Digital Systems, Design, 2001. Proceedings. Euromicro Symposium on, 2001, pp. 430 -436.
J. - T. Li and Marek-Sadowska, M., Global Routing for Gate Array, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 3, pp. 298 - 307, 1984.
C. - C. Tsai and Marek-Sadowska, M., Generalized Reed-Muller forms as a tool to detect symmetries, Computers, IEEE Transactions on, vol. 45, pp. 33 -40, 1996.
K. Wang, Ran, Y., Jiang, H., and Marek-Sadowska, M., General skew constrained clock network sizing based on sequential linear programming, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, pp. 773 - 782, 2005.
M. Marek-Sadowska and Kuh, E. S., General channel-routing algorithm, Electronic Circuits and Systems, IEE Proceedings G, vol. 130, pp. 83 -88, 1983.
T. Xiao and Marek-Sadowska, M., Gate sizing to eliminate crosstalk induced timing violation, in Computer Design, 2001. ICCD 2001. Proceedings. 2001 International Conference on, 2001, pp. 186 -191.
B. Hu, Watanabe, Y., and Marek-Sadowska, M., Gain-based technology mapping for discrete-size cell libraries, in Design Automation Conference, 2003. Proceedings, 2003, pp. 574 - 579.
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D. Chang, Lee, T. - C., Cheng, K. - T., and Marek-Sadowska, M., Functional scan chain testing, in Design, Automation and Test in Europe, 1998., Proceedings, 1998, pp. 278 -283.
T. Xiao and Marek-Sadowska, M., Functional correlation analysis in crosstalk induced critical paths identification, in Design Automation Conference, 2001. Proceedings, 2001, pp. 653 - 656.
A. Singh and Marek-Sadowska, M., FPGA interconnect planning, in SLIP '02: Proceedings of the 2002 international workshop on System-level interconnect prediction, 2002, pp. 23–30.
M. Pedram, Marek-Sadowska, M., and Kuh, E. S., Floorplanning with pin assignment, in Computer-Aided Design, 1990. ICCAD-90. Digest of Technical Papers., 1990 IEEE International Conference on, 1990, pp. 98 -101.
B. Hu and Marek-Sadowska, M., Fine granularity clustering-based placement, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 23, pp. 527 - 536, 2004.

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