Publications

Found 231 results
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W. Maly, Yi-Wei Lin, and Marek-Sadowska, M., “OPC-Free and Minimally Irregular IC Design Style”, in Design Automation Conference, 2007. DAC '07. 44th ACM/IEEE, 2007, pp. 954 -957.
W. Maly, Singh, N., Chen, Z., Shen, N., Li, X., Pfitzner, A., Kasprowicz, D., Kuzmicz, W., Yi-Wei Lin, and Marek-Sadowska, M., “Twin gate, vertical slit FET (VeSFET) for highly periodic layout and 3D integration”, in Mixed Design of Integrated Circuits and Systems (MIXDES), 2011 Proceedings of the 18th International Conference, 2011, pp. 145 -150.
F. Makedon and Marek-Sadowska, M., “Analysis of Heuristic Reasoning for the Visualization of CAD Quadratic”, in ICCAL '89: Proceedings of the 2nd International Conference on Computer Assisted Learning, 1989, pp. 359–378.
L. Macchiarulo, Shu, S. - M., and Marek-Sadowska, M., “Pipelining sequential circuits with wave steering”, Computers, IEEE Transactions on, vol. 53, pp. 1205 - 1210, 2004.
L. Macchiarulo, Shu, S. - M., and Marek-Sadowska, M., “Wave steered FSMs”, in Design, Automation and Test in Europe Conference and Exhibition 2000. Proceedings, 2000, pp. 270 -276.
L. Macchiarulo and Marek-Sadowska, M., “Wave-steering one-hot encoded FSMs”, in DAC '00: Proceedings of the 37th Annual Design Automation Conference, 2000, pp. 357–360.
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Q. Liu and Marek-Sadowska, M., “Pre-layout wire length and congestion estimation”, in Design Automation Conference, 2004. Proceedings. 41st, 2004, pp. 582 -587.
Q. Liu and Marek-Sadowska, M., “Wire length prediction-based technology mapping and fanout optimization”, in ISPD '05: Proceedings of the 2005 international symposium on Physical design, 2005, pp. 145–151.
Q. Liu and Marek-Sadowska, M., “A study of netlist structure and placement efficiency”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, pp. 762 - 772, 2005.
Q. Liu and Marek-Sadowska, M., “A congestion-driven placement framework with local congestion prediction”, in GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI, 2005, pp. 488–493.
Q. Liu and Marek-Sadowska, M., “Semi-individual wire-length prediction with application to logic synthesis”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 25, pp. 611 - 624, 2006.
Q. Liu and Marek-Sadowska, M., “Pre-layout physical connectivity prediction with application in clustering-based placement”, in Computer Design: VLSI in Computers and Processors, 2005. ICCD 2005. Proceedings. 2005 IEEE International Conference on, 2005, pp. 31 - 37.
Q. Liu, Hu, B., and Marek-Sadowska, M., “Wire length prediction in constraint driven placement”, in SLIP '03: Proceedings of the 2003 international workshop on System-level interconnect prediction, 2003, pp. 99–105.
Q. Liu, Hu, B., and Marek-Sadowska, M., “Individual wire-length prediction with application to timing-driven placement”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 12, pp. 1004 -1014, 2004.
C. - C. Lin, Chen, K. - C., and Marek-Sadowska, M., “Logic synthesis for engineering change”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 18, pp. 282 -292, 1999.
C. - C. Lin, Marek-Sadowska, M., Lee, T. - C., and Chen, K. - C., “Cost-free scan: a low-overhead scan path design”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 17, pp. 852 -861, 1998.
C. - C. Lin and Marek-Sadowska, M., “On designing universal logic blocks and their application to FPGA design”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 16, pp. 519 -527, 1997.
C. - C. Lin, Chen, K. - C., Cheng, D. I., and Marek-Sadowska, M., “Logic rectification and synthesis for engineering change”, in Design Automation Conference, 1995. Proceedings of the ASP-DAC '95/CHDL '95/VLSI '95., IFIP International Conference on Hardware Description Languages; IFIP International Conference on Very Large Scale Integration., Asian and South Pacific, 1995, pp. 301 -309.
S. Lin, Marek-Sadowska, M., and Kuh, E. S., “SWEC: a stepwise equivalent conductance timing simulator for CMOS VLSI circuits”, in Design Automation. EDAC., Proceedings of the European Conference on, 1991, pp. 142 -148.
C. - C. Lin, Chang, D., Wu, Y. - L., and Marek-Sadowska, M., “Time-multiplexed routing resources for FPGA design”, in Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996, 1996, pp. 152 -155.
Yi-Wei Lin, Marek-Sadowska, M., and Maly, W., “Transistor-level layout of high-density regular circuits”, in ISPD '09: Proceedings of the 2009 international symposium on Physical design, 2009, pp. 83–90.
S. Lin and Marek-Sadowska, M., “An accurate and efficient delay model for CMOS gates in switch-level timing analysis”, in Circuits and Systems, 1990., IEEE International Symposium on, 1990, pp. 856 -860 vol.2.
C. - C. Lin, Marek-Sadowska, M., Cheng, K. - T., and Lee, T. - C., “Scan paths through functional logic”, in Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996, 1996, pp. 487 -490.
Yi-Wei Lin, Marek-Sadowska, M., Maly, W., Pfitzner, A., and Kasprowicz, D., “Is there always performance overhead for regular fabric?”, in Computer Design, 2008. ICCD 2008. IEEE International Conference on, 2008, pp. 557 -562.
C. - C. Lin, Marek-Sadowska, M., and Gatlin, D., “Universal Logic Gate For Fpga Design”, in Computer-Aided Design, 1994., IEEE/ACM International Conference on, 1994, pp. 164 -168.

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