Publications

Found 228 results
Filters: Author is Malgorzata Marek-Sadowska  [Clear All Filters]
2003
A. Mukherjee and Marek-Sadowska, M., Clock and power gating with timing closure, Design Test of Computers, IEEE, vol. 20, pp. 32 - 39, 2003.
L. H. Chen and Marek-Sadowska, M., Closed-Form Crosstalk Noise Delay Metrics, Analog Integr. Circuits Signal Process., vol. 35, pp. 143–156, 2003.
M. - F. Hsiao, Marek-Sadowska, M., and Chen, S. - J., A crosstalk aware two-pin net router, in Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on, 2003, vol. 5, p. V-485 - V-488 vol.5.
Y. Ran and Marek-Sadowska, M., Crosstalk noise in FPGAs, in Design Automation Conference, 2003. Proceedings, 2003, pp. 944 - 949.
C. - Y. Yeh and Marek-Sadowska, M., Delay budgeting in sequential circuit with application on FPGA placement, in Design Automation Conference, 2003. Proceedings, 2003, pp. 202 - 207.
B. Hu and Marek-Sadowska, M., Fine granularity clustering for large scale placement problems, in ISPD '03: Proceedings of the 2003 international symposium on Physical design, 2003, pp. 67–74.
B. Hu, Watanabe, Y., and Marek-Sadowska, M., Gain-based technology mapping for discrete-size cell libraries, in Design Automation Conference, 2003. Proceedings, 2003, pp. 574 - 579.
M. - F. Hsiao, Marek-Sadowska, M., and Chen, S. - J., Minimizing coupling jitter by buffer resizing for coupled clock networks, in Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on, 2003, vol. 5, p. V-509 - V-512 vol.5.
M. - F. Hsiao, Marek-Sadowska, M., and Chen, S. - J., Minimizing inter-clock coupling jitter, in Quality Electronic Design, 2003. Proceedings. Fourth International Symposium on, 2003, pp. 333 - 338.
C. - Y. Yeh and Marek-Sadowska, M., Minimum-area sequential budgeting for FPGA, in Computer Aided Design, 2003. ICCAD-2003. International Conference on, 2003, pp. 813 - 817.
C. - K. Tsai and Marek-Sadowska, M., Modeling crosstalk induced delay, in Quality Electronic Design, 2003. Proceedings. Fourth International Symposium on, 2003, pp. 189 - 194.
Z. Wang, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., Multiple fault diagnosis using n-detection tests, in Computer Design, 2003. Proceedings. 21st International Conference on, 2003, pp. 198 - 201.
C. - W. Chang, Hsiao, M. - F., and Marek-Sadowska, M., A new reasoning scheme for efficient redundancy addition and removal, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 22, pp. 945 - 951, 2003.
K. Wang and Marek-Sadowska, M., On-chip power supply network optimization using multigrid-based technique, in Design Automation Conference, 2003. Proceedings, 2003, pp. 113 - 118.
A. Singh, Mukherjee, A., Macchiarulo, L., and Marek-Sadowska, M., PITIA: an FPGA for throughput-intensive applications, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 11, pp. 354 -363, 2003.
K. Wang and Marek-Sadowska, M., Power/ground mesh area optimization using multigrid-based technique [IC design], in Design, Automation and Test in Europe Conference and Exhibition, 2003, 2003, pp. 850 - 855.
B. Hu, Jiang, H., Liu, Q., and Marek-Sadowska, M., Synthesis and placement flow for gain-based programmable regular fabrics, in ISPD '03: Proceedings of the 2003 international symposium on Physical design, 2003, pp. 197–203.
D. Chai, Kondratyev, A., Ran, Y., Tseng, K., Watanabe, Y., and Marek-Sadowska, M., Temporofunctional crosstalk noise analysis, in Design Automation Conference, 2003. Proceedings, 2003, pp. 860 - 863.
A. Mukherjee and Marek-Sadowska, M., Wave steering to integrate logic and physical syntheses, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 11, pp. 105 -120, 2003.
B. Hu and Marek-Sadowska, M., Wire length prediction based clustering and its application in placement, in Design Automation Conference, 2003. Proceedings, 2003, pp. 800 - 805.
Q. Liu, Hu, B., and Marek-Sadowska, M., Wire length prediction in constraint driven placement, in SLIP '03: Proceedings of the 2003 international workshop on System-level interconnect prediction, 2003, pp. 99–105.
2004
K. Wang and Marek-Sadowska, M., Buffer sizing for clock power minimization subject to general skew constraints, in Design Automation Conference, 2004. Proceedings. 41st, 2004, pp. 159 -164.
K. Wang and Marek-Sadowska, M., Clock network sizing via sequential linear programming with time-domain analysis, in ISPD '04: Proceedings of the 2004 international symposium on Physical design, 2004, pp. 182–189.
Z. Wang, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., Delay fault diagnosis using timing information, in Quality Electronic Design, 2004. Proceedings. 5th International Symposium on, 2004, pp. 485 - 490.
Y. Ran and Marek-Sadowska, M., Designing a via-configurable regular fabric, in Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004, 2004, pp. 423 - 426.

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