Publications
“Wave steering to integrate logic and physical syntheses”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 11, pp. 105 -120, 2003.
, “Clock and power gating with timing closure”, Design Test of Computers, IEEE, vol. 20, pp. 32 - 39, 2003.
, “Wave steering in YADDs: a novel non-iterative synthesis and layout technique”, in Design Automation Conference, 1999. Proceedings. 36th, 1999, pp. 466 -471.
, “Sizing power/ground meshes for clocking and computing circuit components”, in Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings, 2002, pp. 176 -183.
, “Low power, high throughput network-on-chip fabric for 3D multicore processors”, in Computer Design (ICCD), 2011 IEEE 29th International Conference on, 2011, pp. 453 -454.
, “Layout effects in fine grain 3D integrated regular microprocessor blocks”, in Design Automation Conference (DAC), 2011 48th ACM/EDAC/IEEE, 2011, pp. 639 -644.
, “Statistical static timing analysis flow for transistor level macros in a microprocessor”, in Quality Electronic Design (ISQED), 2010 11th International Symposium on, 2010, pp. 163 -170.
, “A Low Energy Network-on-Chip Fabric for 3-D Multi-Core Architectures”, Emerging and Selected Topics in Circuits and Systems, IEEE Journal on, vol. 2, pp. 266 -277, 2012.
, “Interconnect complexity-aware FPGA placement using Rent's rule”, in SLIP '01: Proceedings of the 2001 international workshop on System-level interconnect prediction, 2001, pp. 115–121.
, “Floorplanning with pin assignment”, in Computer-Aided Design, 1990. ICCAD-90. Digest of Technical Papers., 1990 IEEE International Conference on, 1990, pp. 98 -101.
, “Decomposition of multiple-valued relations”, in Multiple-Valued Logic, 1997. Proceedings., 1997 27th International Symposium on, 1997, pp. 13 -18.
, “Can pin access limit the footprint scaling?”, in Proceedings of the 49th Annual Design Automation Conference, 2012, pp. 1100–1106.
, “Vertical Slit Field Effect Transistor in ultra-low power applications”, in Quality Electronic Design (ISQED), 2012 13th International Symposium on, 2012, pp. 384 -390.
, “On designing via-configurable cell blocks for regular fabrics”, in Design Automation Conference, 2004. Proceedings. 41st, 2004, pp. 198 -203.
, “Crosstalk noise in FPGAs”, in Design Automation Conference, 2003. Proceedings, 2003, pp. 944 - 949.
, “Eliminating false positives in crosstalk noise analysis”, in Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings, 2004, vol. 2, pp. 1192 - 1197 Vol.2.
, “An integrated design flow for a via-configurable gate array”, in Computer Aided Design, 2004. ICCAD-2004. IEEE/ACM International Conference on, 2004, pp. 582 - 589.
, “Eliminating false positives in crosstalk noise analysis”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, pp. 1406 - 1419, 2005.
, “Designing a via-configurable regular fabric”, in Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004, 2004, pp. 423 - 426.
, “The magic of a via-configurable regular fabric”, in Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. IEEE International Conference on, 2004, pp. 338 - 343.
, “Via-Configurable Routing Architectures and Fast Design Mappability Estimation for Regular Fabrics”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 14, pp. 998 -1009, 2006.
, “Designing via-configurable logic blocks for regular fabric”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 14, pp. 1 -14, 2006.
, “Via-configurable routing architectures and fast design mappability estimation for regular fabrics”, in Computer-Aided Design, 2005. ICCAD-2005. IEEE/ACM International Conference on, 2005, pp. 25 - 32.
, “Interconnect pipelining in a throughput-intensive FPGA architecture”, in FPGA '01: Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays, 2001, pp. 153–160.
, “FPGA interconnect planning”, in SLIP '02: Proceedings of the 2002 international workshop on System-level interconnect prediction, 2002, pp. 23–30.
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