Publications

Found 231 results
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A. Singh, Parthasarathy, G., and Marek-Sadowska, M., “Efficient circuit clustering for area and power reduction in FPGAs”, ACM Trans. Des. Autom. Electron. Syst., vol. 7, pp. 643–663, 2002.
A. Singh and Marek-Sadowska, M., “Efficient circuit clustering for area and power reduction in FPGAs”, in FPGA '02: Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays, 2002, pp. 59–66.
A. Singh, Mukherjee, A., and Marek-Sadowska, M., “Latency and latch count minimization in wave steered circuits”, in Design Automation Conference, 2001. Proceedings, 2001, pp. 383 - 388.
A. Singh, Mukherjee, A., and Marek-Sadowska, M., “Interconnect pipelining in a throughput-intensive FPGA architecture”, in FPGA '01: Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays, 2001, pp. 153–160.
A. Singh, Parthasarathy, G., and Marek-Sadowska, M., “Interconnect resource-aware placement for hierarchical FPGAs”, in Computer Aided Design, 2001. ICCAD 2001. IEEE/ACM International Conference on, 2001, pp. 132 -136.
A. Singh and Marek-Sadowska, M., “FPGA interconnect planning”, in SLIP '02: Proceedings of the 2002 international workshop on System-level interconnect prediction, 2002, pp. 23–30.
A. Singh and Marek-Sadowska, M., “Circuit clustering using graph coloring”, in ISPD '99: Proceedings of the 1999 international symposium on Physical design, 1999, pp. 164–169.
Y. - S. Su, Wang, D. - C., Chang, S. - C., and Marek-Sadowska, M., “An Efficient Mechanism for Performance Optimization of Variable-Latency Designs”, in Design Automation Conference, 2007. DAC '07. 44th ACM/IEEE, 2007, pp. 976 -981.
Y. - S. Su, Wang, D. - C., Chang, S. - C., and Marek-Sadowska, M., “Performance Optimization Using Variable-Latency Design Style”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 19, pp. 1874 -1883, 2011.
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T. T. - K. Tarng, Marek-Sadowska, M., and Kuh, E. S., “An Efficient Single-Row Routing Algorithm”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 3, pp. 178 - 183, 1984.
A. Todri and Marek-Sadowska, M., “A study of reliability issues in clock distribution networks”, in Computer Design, 2008. ICCD 2008. IEEE International Conference on, 2008, pp. 101 -106.
A. Todri, Marek-Sadowska, M., Maire, F., and Matheron, C., “A study of decoupling capacitor effectiveness in power and ground grid networks”, in Quality of Electronic Design, 2009. ISQED 2009. Quality Electronic Design, 2009, pp. 653 -658.
A. Todri, Chang, S. - C., and Marek-Sadowska, M., “Electromigration and voltage drop aware power grid optimization for power gated ICs”, in Low Power Electronics and Design (ISLPED), 2007 ACM/IEEE International Symposium on, 2007, pp. 391 -394.
A. Todri and Marek-Sadowska, M., “Reliability Analysis and Optimization of Power-Gated ICs”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 19, pp. 457 -468, 2011.
A. Todri, Marek-Sadowska, M., and Chang, S. - C., “Analysis and optimization of power-gated ICs with multiple power gating configurations”, in Computer-Aided Design, 2007. ICCAD 2007. IEEE/ACM International Conference on, 2007, pp. 783 -790.
A. Todri and Marek-Sadowska, M., “Electromigration study of power-gated grids”, in ISLPED '09: Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design, 2009, pp. 315–318.
A. Todri and Marek-Sadowska, M., “Power Delivery for Multicore Systems”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 19, pp. 2243 -2255, 2011.
A. Todri, Marek-Sadowska, M., and Kozhaya, J., “Power supply noise aware workload assignment for multi-core systems”, in Computer-Aided Design, 2008. ICCAD 2008. IEEE/ACM International Conference on, 2008, pp. 330 -337.
K. - H. Tsai, Rajski, J., and Marek-Sadowska, M., “Star test: the theory and its applications”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 19, pp. 1052 -1064, 2000.
C. - C. Tsai and Marek-Sadowska, M., “Boolean Matching Using Generalized Reed-Muller Forms”, in Design Automation, 1994. 31st Conference on, 1994, pp. 339 - 344.
K. - H. Tsai, Tompson, R., Rajski, J., and Marek-Sadowska, M., “STAR-ATPG: a high speed test pattern generator for large scan designs”, in Test Conference, 1999. Proceedings. International, 1999, pp. 1021 -1030.
C. - C. Tsai and Marek-Sadowska, M., “Efficient minimization algorithms for fixed polarity AND/XOR canonical networks”, in VLSI, 1993. 'Design Automation of High Performance VLSI Systems', Proceedings., Third Great Lakes Symposium on, 1993, pp. 76 -79.
C. - C. Tsai and Marek-Sadowska, M., “Multilevel logic synthesis for arithmetic functions”, in Design Automation Conference Proceedings 1996, 33rd, 1996, pp. 242 -247.
C. - K. Tsai and Marek-Sadowska, M., “An interconnect insensitive linear time-varying driver model for static timing analysis”, in Quality of Electronic Design, 2005. ISQED 2005. Sixth International Symposium on, 2005, pp. 654 - 661.
C. - C. Tsai and Marek-Sadowska, M., “Minimisation of fixed-polarity AND/XOR canonical networks”, Computers and Digital Techniques, IEE Proceedings -, vol. 141, pp. 369 -374, 1994.

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