Publications

Found 228 results
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Conference Paper
A. Singh, Mukherjee, A., and Marek-Sadowska, M., Latency and latch count minimization in wave steered circuits, in Design Automation Conference, 2001. Proceedings, 2001, pp. 383 - 388.
A. Singh, Parthasarathy, G., and Marek-Sadowska, M., Interconnect resource-aware placement for hierarchical FPGAs, in Computer Aided Design, 2001. ICCAD 2001. IEEE/ACM International Conference on, 2001, pp. 132 -136.
A. Singh, Mukherjee, A., and Marek-Sadowska, M., Interconnect pipelining in a throughput-intensive FPGA architecture, in FPGA '01: Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays, 2001, pp. 153–160.
C. - K. Tsai and Marek-Sadowska, M., An interconnect insensitive linear time-varying driver model for static timing analysis, in Quality of Electronic Design, 2005. ISQED 2005. Sixth International Symposium on, 2005, pp. 654 - 661.
G. Parthasarathy, Marek-Sadowska, M., Mukherjee, A., and Singh, A., Interconnect complexity-aware FPGA placement using Rent's rule, in SLIP '01: Proceedings of the 2001 international workshop on System-level interconnect prediction, 2001, pp. 115–121.
Y. Ran and Marek-Sadowska, M., An integrated design flow for a via-configurable gate array, in Computer Aided Design, 2004. ICCAD-2004. IEEE/ACM International Conference on, 2004, pp. 582 - 589.
C. - W. Chang, Hu, B., and Marek-Sadowska, M., In-place delay constrained power optimization using functional symmetries, in Design, Automation and Test in Europe, 2001. Conference and Exhibition 2001. Proceedings, 2001, pp. 377 -382.
L. H. Chen and Marek-Sadowska, M., Incremental delay change due to crosstalk noise, in ISPD '02: Proceedings of the 2002 international symposium on Physical design, 2002, pp. 120–125.
Y. - L. Wu and Marek-Sadowska, M., Graph based analysis of FPGA routing, in Design Automation Conference, 1993, with EURO-VHDL '93. Proceedings EURO-DAC '93. European, 1993, pp. 104 -109.
N. Funabiki, Singh, A., Mukherjee, A., and Marek-Sadowska, M., A global routing technique for wave-steered design methodology, in Digital Systems, Design, 2001. Proceedings. Euromicro Symposium on, 2001, pp. 430 -436.
T. Xiao and Marek-Sadowska, M., Gate sizing to eliminate crosstalk induced timing violation, in Computer Design, 2001. ICCD 2001. Proceedings. 2001 International Conference on, 2001, pp. 186 -191.
B. Hu, Watanabe, Y., and Marek-Sadowska, M., Gain-based technology mapping for discrete-size cell libraries, in Design Automation Conference, 2003. Proceedings, 2003, pp. 574 - 579.
D. Chang, Lee, T. - C., Cheng, K. - T., and Marek-Sadowska, M., Functional scan chain testing, in Design, Automation and Test in Europe, 1998., Proceedings, 1998, pp. 278 -283.
T. Xiao and Marek-Sadowska, M., Functional correlation analysis in crosstalk induced critical paths identification, in Design Automation Conference, 2001. Proceedings, 2001, pp. 653 - 656.
A. Singh and Marek-Sadowska, M., FPGA interconnect planning, in SLIP '02: Proceedings of the 2002 international workshop on System-level interconnect prediction, 2002, pp. 23–30.
M. Pedram, Marek-Sadowska, M., and Kuh, E. S., Floorplanning with pin assignment, in Computer-Aided Design, 1990. ICCAD-90. Digest of Technical Papers., 1990 IEEE International Conference on, 1990, pp. 98 -101.
B. Hu and Marek-Sadowska, M., Fine granularity clustering for large scale placement problems, in ISPD '03: Proceedings of the 2003 international symposium on Physical design, 2003, pp. 67–74.
C. - W. Chang, Cheng, C. - K., Suaris, P., and Marek-Sadowska, M., Fast post-placement rewiring using easily detectable functional symmetries, in Design Automation Conference, 2000. Proceedings 2000. 37th, 2000, pp. 286 -289.
S. - C. Chang, Van Ginneken, L. P. P. P., and Marek-Sadowska, M., Fast Boolean optimization by rewiring, in Computer-Aided Design, 1996. ICCAD-96. Digest of Technical Papers., 1996 IEEE/ACM International Conference on, 1996, pp. 262 -269.
J. - Y. Wuu, Pikus, F. G., and Marek-Sadowska, M., Fast and simple modeling of non-rectangular transistors, in Society of Photo-Optical Instrumentation Engineers (SPIE) Conference Series, 2008, vol. 7122.
S. Lin and Marek-Sadowska, M., A fast and efficient algorithm for determining fanout trees in large networks, in Design Automation. EDAC., Proceedings of the European Conference on, 1991, pp. 539 -544.
B. Hu and Marek-Sadowska, M., FAR: fixed-points addition & relaxation based placement, in ISPD '02: Proceedings of the 2002 international symposium on Physical design, 2002, pp. 161–166.
Y. - M. Kuo, Chang, Y. - T., Chang, S. - C., and Marek-Sadowska, M., Engineering change using spare cells with constant insertion, in ICCAD '07: Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, 2007, pp. 544–547.
Y. Ran, Kondratyev, A., Watanabe, Y., and Marek-Sadowska, M., Eliminating false positives in crosstalk noise analysis, in Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings, 2004, vol. 2, pp. 1192 - 1197 Vol.2.
A. Todri and Marek-Sadowska, M., Electromigration study of power-gated grids, in ISLPED '09: Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design, 2009, pp. 315–318.

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