Publications

Found 231 results
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Yi-Wei Lin, Marek-Sadowska, M., and Maly, W., On Cell Layout-Performance Relationships in VeSFET-Based, High-Density Regular Circuits, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 30, pp. 229 -241, 2011.
C. - C. Lin, Chang, D., Wu, Y. - L., and Marek-Sadowska, M., Time-multiplexed routing resources for FPGA design, in Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996, 1996, pp. 152 -155.
S. Lin, Marek-Sadowska, M., and Kuh, E. S., SWEC: a stepwise equivalent conductance timing simulator for CMOS VLSI circuits, in Design Automation. EDAC., Proceedings of the European Conference on, 1991, pp. 142 -148.
Yi-Wei Lin, Marek-Sadowska, M., and Maly, W., Transistor-level layout of high-density regular circuits, in ISPD '09: Proceedings of the 2009 international symposium on Physical design, 2009, pp. 83–90.
S. Lin and Marek-Sadowska, M., An accurate and efficient delay model for CMOS gates in switch-level timing analysis, in Circuits and Systems, 1990., IEEE International Symposium on, 1990, pp. 856 -860 vol.2.
C. - C. Lin, Chen, K. - C., and Marek-Sadowska, M., Logic synthesis for engineering change, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 18, pp. 282 -292, 1999.
C. - C. Lin, Marek-Sadowska, M., Lee, T. - C., and Chen, K. - C., Cost-free scan: a low-overhead scan path design, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 17, pp. 852 -861, 1998.
C. - C. Lin, Marek-Sadowska, M., Cheng, K. - T., and Lee, T. - C., Scan paths through functional logic, in Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996, 1996, pp. 487 -490.
C. - C. Lin and Marek-Sadowska, M., On designing universal logic blocks and their application to FPGA design, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 16, pp. 519 -527, 1997.
C. - C. Lin, Marek-Sadowska, M., and Gatlin, D., Universal Logic Gate For Fpga Design, in Computer-Aided Design, 1994., IEEE/ACM International Conference on, 1994, pp. 164 -168.
S. Lin, Kuh, E. S., and Marek-Sadowska, M., Stepwise equivalent conductance circuit simulation technique, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 12, pp. 672 -683, 1993.
Li, Di-an, Marek-Sadowska, M., and Lee, B., On-chip em-sensitive interconnect structures, in SLIP '10: Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction, 2010, pp. 43–50.
Li, Di-an and Marek-Sadowska, M., Variation-aware electromigration analysis of power/ground networks, in Computer-Aided Design (ICCAD), 2011 IEEE/ACM International Conference on, 2011, pp. 571 -576.
J. - T. Li and Marek-Sadowska, M., Global Routing for Gate Array, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 3, pp. 298 - 307, 1984.
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Y. - M. Kuo, Chang, Y. - T., Chang, S. - C., and Marek-Sadowska, M., Spare Cells With Constant Insertion for Engineering Change, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 28, pp. 456 -460, 2009.
Y. - M. Kuo, Chang, Y. - T., Chang, S. - C., and Marek-Sadowska, M., Engineering change using spare cells with constant insertion, in ICCAD '07: Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, 2007, pp. 544–547.
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H. Jiang, Wang, K., and Marek-Sadowska, M., Clock skew bounds estimation under power supply and process variations, in GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI, 2005, pp. 332–336.
H. Jiang, Marek-Sadowska, M., and Nassif, S. R., Benefits and costs of power-gating technique, in 2005 IEEE International Conference on Computer Design , 2005, pp. 559 - 566.
H. Jiang and Marek-Sadowska, M., Power gating scheduling for power/ground noise reduction, in Design Automation Conference, 2008. DAC 2008. 45th ACM/IEEE, 2008, pp. 980 -985.
H. Jiang and Marek-Sadowska, M., Power/Ground Supply Network Optimization for Power-Gating, in Computer Design, 2006. ICCD 2006. International Conference on, 2006, pp. 332 -337.
H. Jiang and Marek-Sadowska, M., Power-Gating Aware Floorplanning, in Quality Electronic Design, 2007. ISQED '07. 8th International Symposium on, 2007, pp. 853 -860.
Y. - M. Jiang, Krstic, A., Cheng, K. - T., and Marek-Sadowska, M., Post-layout Logic Restructuring For Performance Optimization, in Design Automation Conference, 1997. Proceedings of the 34th, 1997, pp. 662 -665.
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B. Hu and Marek-Sadowska, M., Congestion minimization during placement without estimation, in Computer Aided Design, 2002. ICCAD 2002. IEEE/ACM International Conference on, 2002, pp. 739 - 745.
B. Hu and Marek-Sadowska, M., Multilevel expansion-based VLSI placement with blockages, in Computer Aided Design, 2004. ICCAD-2004. IEEE/ACM International Conference on, 2004, pp. 558-564.
B. Hu and Marek-Sadowska, M., Fine granularity clustering for large scale placement problems, in ISPD '03: Proceedings of the 2003 international symposium on Physical design, 2003, pp. 67–74.

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