Publications

Found 231 results
2004
Y. Ran and Marek-Sadowska, M., On designing via-configurable cell blocks for regular fabrics, in Design Automation Conference, 2004. Proceedings. 41st, 2004, pp. 198 -203.
Z. Wang, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., Diagnosis of hold time defects, in Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. IEEE International Conference on, 2004, pp. 192 - 199.
Y. Ran, Kondratyev, A., Watanabe, Y., and Marek-Sadowska, M., Eliminating false positives in crosstalk noise analysis, in Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings, 2004, vol. 2, pp. 1192 - 1197 Vol.2.
C. - W. Chang, Hsiao, M. - F., Hu, B., Wang, K., Marek-Sadowska, M., Cheng, C. - K., and Chen, S. - J., Fast postplacement optimization using functional symmetries, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 23, pp. 102 - 118, 2004.
B. Hu and Marek-Sadowska, M., Fine granularity clustering-based placement, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 23, pp. 527 - 536, 2004.
Q. Liu, Hu, B., and Marek-Sadowska, M., Individual wire-length prediction with application to timing-driven placement, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 12, pp. 1004 -1014, 2004.
Y. Ran and Marek-Sadowska, M., An integrated design flow for a via-configurable gate array, in Computer Aided Design, 2004. ICCAD-2004. IEEE/ACM International Conference on, 2004, pp. 582 - 589.
Y. Ran and Marek-Sadowska, M., The magic of a via-configurable regular fabric, in Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. IEEE International Conference on, 2004, pp. 338 - 343.
B. Hu and Marek-Sadowska, M., Multilevel expansion-based VLSI placement with blockages, in Computer Aided Design, 2004. ICCAD-2004. IEEE/ACM International Conference on, 2004, pp. 558-564.
L. Macchiarulo, Shu, S. - M., and Marek-Sadowska, M., Pipelining sequential circuits with wave steering, Computers, IEEE Transactions on, vol. 53, pp. 1205 - 1210, 2004.
K. Wang and Marek-Sadowska, M., Potential slack budgeting with clock skew optimization, in Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. IEEE International Conference on, 2004, pp. 265 - 271.
Q. Liu and Marek-Sadowska, M., Pre-layout wire length and congestion estimation, in Design Automation Conference, 2004. Proceedings. 41st, 2004, pp. 582 -587.
C. - Y. Yeh and Marek-Sadowska, M., Sequential delay budgeting with interconnect prediction, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 12, pp. 1028 -1037, 2004.
2005
H. Jiang, Marek-Sadowska, M., and Nassif, S. R., Benefits and costs of power-gating technique, in 2005 IEEE International Conference on Computer Design , 2005, pp. 559 - 566.
H. Jiang, Wang, K., and Marek-Sadowska, M., Clock skew bounds estimation under power supply and process variations, in GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI, 2005, pp. 332–336.
Q. Liu and Marek-Sadowska, M., A congestion-driven placement framework with local congestion prediction, in GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI, 2005, pp. 488–493.
Z. Wang, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., Delay-fault diagnosis using timing information, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, pp. 1315 - 1325, 2005.
Y. Ran, Kondratyev, A., Tseng, K., Watanabe, Y., and Marek-Sadowska, M., Eliminating false positives in crosstalk noise analysis, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, pp. 1406 - 1419, 2005.
K. Wang, Ran, Y., Jiang, H., and Marek-Sadowska, M., General skew constrained clock network sizing based on sequential linear programming, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, pp. 773 - 782, 2005.
C. - K. Tsai and Marek-Sadowska, M., An interconnect insensitive linear time-varying driver model for static timing analysis, in Quality of Electronic Design, 2005. ISQED 2005. Sixth International Symposium on, 2005, pp. 654 - 661.
B. Hu, Zeng, Y., and Marek-Sadowska, M., mFAR: fixed-points-addition-based VLSI placement algorithm, in ISPD '05: Proceedings of the 2005 international symposium on Physical design, 2005, pp. 239–241.
B. Hu and Marek-Sadowska, M., Multilevel fixed-point-addition-based VLSI placement, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, pp. 1188 - 1203, 2005.
K. Wang and Marek-Sadowska, M., On-chip power-supply network optimization using multigrid-based technique, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, pp. 407 - 417, 2005.
Q. Liu and Marek-Sadowska, M., Pre-layout physical connectivity prediction with application in clustering-based placement, in Computer Design: VLSI in Computers and Processors, 2005. ICCD 2005. Proceedings. 2005 IEEE International Conference on, 2005, pp. 31 - 37.
C. - Y. Yeh and Marek-Sadowska, M., Skew-programmable clock design for FPGA and skew-aware placement, in FPGA '05: Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays, 2005, pp. 33–40.

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