Publications

Found 228 results
Filters: Author is Malgorzata Marek-Sadowska  [Clear All Filters]
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 
P
L. Macchiarulo, Shu, S. - M., and Marek-Sadowska, M., Pipelining sequential circuits with wave steering, Computers, IEEE Transactions on, vol. 53, pp. 1205 - 1210, 2004.
A. Singh, Mukherjee, A., Macchiarulo, L., and Marek-Sadowska, M., PITIA: an FPGA for throughput-intensive applications, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 11, pp. 354 -363, 2003.
Y. - M. Jiang, Krstic, A., Cheng, K. - T., and Marek-Sadowska, M., Post-layout Logic Restructuring For Performance Optimization, in Design Automation Conference, 1997. Proceedings of the 34th, 1997, pp. 662 -665.
S. - C. Chang, Cheng, K. - T., Woo, N. - S., and Marek-Sadowska, M., Postlayout logic restructuring using alternative wires, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 16, pp. 587 -596, 1997.
K. Wang and Marek-Sadowska, M., Potential slack budgeting with clock skew optimization, in Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. IEEE International Conference on, 2004, pp. 265 - 271.
A. Todri and Marek-Sadowska, M., Power Delivery for Multicore Systems, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 19, pp. 2243 -2255, 2011.
A. Vittal and Marek-Sadowska, M., Power Distribution Topology Design, in Design Automation, 1995. DAC '95. 32nd Conference on, 1995, pp. 503 -507.
H. Jiang and Marek-Sadowska, M., Power gating scheduling for power/ground noise reduction, in Design Automation Conference, 2008. DAC 2008. 45th ACM/IEEE, 2008, pp. 980 -985.
A. Vittal and Marek-Sadowska, M., Power Optimal Buffered Clock Tree Design, in Design Automation, 1995. DAC '95. 32nd Conference on, 1995, pp. 497 -502.
A. Todri, Marek-Sadowska, M., and Kozhaya, J., Power supply noise aware workload assignment for multi-core systems, in Computer-Aided Design, 2008. ICCAD 2008. IEEE/ACM International Conference on, 2008, pp. 330 -337.
H. Jiang and Marek-Sadowska, M., Power-Gating Aware Floorplanning, in Quality Electronic Design, 2007. ISQED '07. 8th International Symposium on, 2007, pp. 853 -860.
K. Wang and Marek-Sadowska, M., Power/ground mesh area optimization using multigrid-based technique [IC design], in Design, Automation and Test in Europe Conference and Exhibition, 2003, 2003, pp. 850 - 855.
H. Jiang and Marek-Sadowska, M., Power/Ground Supply Network Optimization for Power-Gating, in Computer Design, 2006. ICCD 2006. International Conference on, 2006, pp. 332 -337.
Q. Liu and Marek-Sadowska, M., Pre-layout physical connectivity prediction with application in clustering-based placement, in Computer Design: VLSI in Computers and Processors, 2005. ICCD 2005. Proceedings. 2005 IEEE International Conference on, 2005, pp. 31 - 37.
Q. Liu and Marek-Sadowska, M., Pre-layout wire length and congestion estimation, in Design Automation Conference, 2004. Proceedings. 41st, 2004, pp. 582 -587.
R
J. - Y. Wuu, Pikus, F. G., Torres, A., and Marek-Sadowska, M., Rapid layout pattern classification, in Design Automation Conference (ASP-DAC), 2011 16th Asia and South Pacific, 2011, pp. 781 -786.
A. Todri and Marek-Sadowska, M., Reliability Analysis and Optimization of Power-Gated ICs, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 19, pp. 457 -468, 2011.
Y. - L. Wu and Marek-Sadowska, M., Routing for array-type FPGA's, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 16, pp. 506 -518, 1997.
Y. - L. Wu and Marek-Sadowska, M., Routing on regular segmented 2-D FPGAs, in Design Automation Conference, 1995. Proceedings of the ASP-DAC '95/CHDL '95/VLSI '95., IFIP International Conference on Hardware Description Languages; IFIP International Conference on Very Large Scale Integration., Asian and South Pacific, 1995, pp. 329 -334.
S
K. - H. Tsai, Rajski, J., and Marek-Sadowska, M., Scan encoded test pattern generation for BIST, in Test Conference, 1997. Proceedings., International, 1997, pp. 548 -556.
C. - C. Lin, Marek-Sadowska, M., Cheng, K. - T., and Lee, T. - C., Scan paths through functional logic, in Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996, 1996, pp. 487 -490.
Q. Liu and Marek-Sadowska, M., Semi-individual wire-length prediction with application to logic synthesis, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 25, pp. 611 - 624, 2006.
C. - Y. Yeh and Marek-Sadowska, M., Sequential delay budgeting with interconnect prediction, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 12, pp. 1028 -1037, 2004.
C. - C. Lin, Chen, K. - C., Marek-Sadowska, M., and Lee, T. - C., Sequential permissible functions and their application to circuit optimization, in European Design and Test Conference, 1996. ED TC 96. Proceedings, 1996, pp. 334 -339.
M. Marek-Sadowska and Tarng, T. T. - K., Single-Layer Routing for VLSI: Analysis and Algorithms, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 2, pp. 246 - 259, 1983.

Pages