Publications

Found 231 results
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 
H
B. Hu and Marek-Sadowska, M., “Wire length prediction based clustering and its application in placement”, in Design Automation Conference, 2003. Proceedings, 2003, pp. 800 - 805.
B. Hu, Jiang, H., Liu, Q., and Marek-Sadowska, M., “Synthesis and placement flow for gain-based programmable regular fabrics”, in ISPD '03: Proceedings of the 2003 international symposium on Physical design, 2003, pp. 197–203.
B. Hu, Watanabe, Y., and Marek-Sadowska, M., “Gain-based technology mapping for discrete-size cell libraries”, in Design Automation Conference, 2003. Proceedings, 2003, pp. 574 - 579.
B. Hu and Marek-Sadowska, M., “FAR: fixed-points addition & relaxation based placement”, in ISPD '02: Proceedings of the 2002 international symposium on Physical design, 2002, pp. 161–166.
B. Hu and Marek-Sadowska, M., “Multilevel fixed-point-addition-based VLSI placement”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, pp. 1188 - 1203, 2005.
B. Hu and Marek-Sadowska, M., “Fine granularity clustering-based placement”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 23, pp. 527 - 536, 2004.
B. Hu and Marek-Sadowska, M., “Congestion minimization during placement without estimation”, in Computer Aided Design, 2002. ICCAD 2002. IEEE/ACM International Conference on, 2002, pp. 739 - 745.
M. - F. Hsiao, Marek-Sadowska, M., and Chen, S. - J., “Crosstalk minimization for multiple clock tree routing”, in Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on, 2002, vol. 1, pp. I - 152-5 vol.1.
M. - F. Hsiao, Marek-Sadowska, M., and Chen, S. - J., “Minimizing coupling jitter by buffer resizing for coupled clock networks”, in Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on, 2003, vol. 5, p. V-509 - V-512 vol.5.
M. - F. Hsiao, Marek-Sadowska, M., and Chen, S. - J., “A crosstalk aware two-pin net router”, in Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on, 2003, vol. 5, p. V-485 - V-488 vol.5.
M. - F. Hsiao, Marek-Sadowska, M., and Chen, S. - J., “Minimizing inter-clock coupling jitter”, in Quality Electronic Design, 2003. Proceedings. Fourth International Symposium on, 2003, pp. 333 - 338.
G
S. Grygiel, Perkowski, M., Marek-Sadowska, M., Luba, T., and Jozwiak, L., “Cube diagram bundles: a new representation of strongly unspecified multiple-valued functions and relations”, in Multiple-Valued Logic, 1997. Proceedings., 1997 27th International Symposium on, 1997, pp. 287 -292.
F
N. Funabiki, Singh, A., Mukherjee, A., and Marek-Sadowska, M., “A global routing technique for wave-steered design methodology”, in Digital Systems, Design, 2001. Proceedings. Euromicro Symposium on, 2001, pp. 430 -436.
D
R. Dutta and Marek-Sadowska, M., “Automatic Sizing of Power/Ground (P/G) Networks in VLSI”, in Design Automation, 1989. 26th Conference on, 1989, pp. 783 - 786.
C
D. I. Cheng, Cheng, K. - T., Wang, D. C., and Marek-Sadowska, M., “A new hybrid methodology for power estimation”, in Design Automation Conference Proceedings 1996, 33rd, 1996, pp. 439 -444.
D. I. Cheng, Lin, C. - C., and Marek-Sadowska, M., “Circuit partitioning with logic perturbation”, in Computer-Aided Design, 1995. ICCAD-95. Digest of Technical Papers., 1995 IEEE/ACM International Conference on, 1995, pp. 650 -655.
D. I. Cheng and Marek-Sadowska, M., “Verifying equivalence of functions with unknown input correspondence”, in Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on, 1993, pp. 81 -85.
D. I. Cheng, Marek-Sadowska, M., and Cheng, K. - T., “Speeding up power estimation by topological analysis”, in Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995, 1995, pp. 623 -626.
D. I. Cheng, Cheng, K. - T., Wang, D. C., and Marek-Sadowska, M., “A hybrid methodology for switching activities estimation”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 17, pp. 357 -366, 1998.
L. H. Chen, Marek-Sadowska, M., and Brewer, F., “Buffer delay change in the presence of power and ground noise”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 11, pp. 461 -473, 2003.
L. H. Chen, Marek-Sadowska, M., and Brewer, F., “Coping with buffer delay change due to power and ground noise”, in Design Automation Conference, 2002. Proceedings. 39th, 2002, pp. 860 - 865.
L. H. Chen and Marek-Sadowska, M., “Incremental delay change due to crosstalk noise”, in ISPD '02: Proceedings of the 2002 international symposium on Physical design, 2002, pp. 120–125.
L. H. Chen and Marek-Sadowska, M., “Efficient closed-form crosstalk delay metrics”, in Quality Electronic Design, 2002. Proceedings. International Symposium on, 2002, pp. 431 - 436.
F. Chen, Mittl, S., Shinosky, M., Swift, A., Kontra, R., Anderson, B., Aitken, J., Wang, Y., Kinser, E., Kumar, M., Wang, Y., Kane, T., Feng, K. D., Henson, W. K., Mocuta, D., and Li, Di-an, “Investigation of emerging middle-of-line poly gate-to-diffusion contact reliability issues”, in Reliability Physics Symposium (IRPS), 2012 IEEE International, 2012, pp. 6A.4.1 -6A.4.9.
L. H. Chen and Marek-Sadowska, M., “Aggressor alignment for worst-case coupling noise”, in ISPD '00: Proceedings of the 2000 international symposium on Physical design, 2000, pp. 48–54.

Pages