Publications

Found 231 results
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Q. Liu and Marek-Sadowska, M., A congestion-driven placement framework with local congestion prediction, in GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI, 2005, pp. 488–493.
B. Hu and Marek-Sadowska, M., Congestion minimization during placement without estimation, in Computer Aided Design, 2002. ICCAD 2002. IEEE/ACM International Conference on, 2002, pp. 739 - 745.
Y. - L. Wu, Tsukiyama, S., and Marek-Sadowska, M., On computational complexity of a detailed routing problem in two dimensional FPGAs, in VLSI, 1994. Design Automation of High Performance VLSI Systems. GLSV '94, Proceedings., Fourth Great Lakes Symposium on, 1994, pp. 70 -75.
L. H. Chen and Marek-Sadowska, M., Closed-form crosstalk noise metrics for physical design applications, in Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings, 2002, pp. 812 - 819.
L. H. Chen and Marek-Sadowska, M., Closed-Form Crosstalk Noise Delay Metrics, Analog Integr. Circuits Signal Process., vol. 35, pp. 143–156, 2003.
A. Vittal, Ha, H., Brewer, F., and Marek-Sadowska, M., Clock skew optimization for ground bounce control, in Computer-Aided Design, 1996. ICCAD-96. Digest of Technical Papers., 1996 IEEE/ACM International Conference on, 1996, pp. 395 -399.
H. Jiang, Wang, K., and Marek-Sadowska, M., Clock skew bounds estimation under power supply and process variations, in GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI, 2005, pp. 332–336.
K. Wang and Marek-Sadowska, M., Clock network sizing via sequential linear programming with time-domain analysis, in ISPD '04: Proceedings of the 2004 international symposium on Physical design, 2004, pp. 182–189.
A. Mukherjee and Marek-Sadowska, M., Clock and power gating with timing closure, Design Test of Computers, IEEE, vol. 20, pp. 32 - 39, 2003.
D. I. Cheng, Lin, C. - C., and Marek-Sadowska, M., Circuit partitioning with logic perturbation, in Computer-Aided Design, 1995. ICCAD-95. Digest of Technical Papers., 1995 IEEE/ACM International Conference on, 1995, pp. 650 -655.
S. - C. Chang, Van Ginneken, L. P. P. P., and Marek-Sadowska, M., Circuit optimization by rewiring, Computers, IEEE Transactions on, vol. 48, pp. 962 -970, 1999.
A. Singh and Marek-Sadowska, M., Circuit clustering using graph coloring, in ISPD '99: Proceedings of the 1999 international symposium on Physical design, 1999, pp. 164–169.
Yi-Wei Lin, Marek-Sadowska, M., and Maly, W., On Cell Layout-Performance Relationships in VeSFET-Based, High-Density Regular Circuits, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 30, pp. 229 -241, 2011.
L. H. Chen, Marek-Sadowska, M., Divecha, R., and Singh, P., Capturing input switching dependency in crosstalk noise modeling, in ASIC/SOC Conference, 2000. Proceedings. 13th Annual IEEE International, 2000, pp. 330 -334.
X. Qiu and Marek-Sadowska, M., Can pin access limit the footprint scaling?, in Proceedings of the 49th Annual Design Automation Conference, 2012, pp. 1100–1106.
B
K. Wang and Marek-Sadowska, M., Buffer sizing for clock power minimization subject to general skew constraints, in Design Automation Conference, 2004. Proceedings. 41st, 2004, pp. 159 -164.
D. Chang and Marek-Sadowska, M., Buffer minimization and time-multiplexed I/O on dynamically reconfigurable FPGAs, in FPGA '97: Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays, 1997, pp. 142–148.
L. H. Chen, Marek-Sadowska, M., and Brewer, F., Buffer delay change in the presence of power and ground noise, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 11, pp. 461 -473, 2003.
C. - C. Tsai and Marek-Sadowska, M., Boolean Matching Using Generalized Reed-Muller Forms, in Design Automation, 1994. 31st Conference on, 1994, pp. 339 - 344.
C. - C. Tsai and Marek-Sadowska, M., Boolean functions classification via fixed polarity Reed-Muller forms, Computers, IEEE Transactions on, vol. 46, pp. 173 -186, 1997.
H. Jiang, Marek-Sadowska, M., and Nassif, S. R., Benefits and costs of power-gating technique, in 2005 IEEE International Conference on Computer Design , 2005, pp. 559 - 566.
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R. Dutta and Marek-Sadowska, M., Automatic Sizing of Power/Ground (P/G) Networks in VLSI, in Design Automation, 1989. 26th Conference on, 1989, pp. 783 - 786.
C. - W. Chang and Marek-Sadowska, M., ATPG-based logic synthesis: an overview, in Computer Aided Design, 2002. ICCAD 2002. IEEE/ACM International Conference on, 2002, pp. 786 - 789.
C. - K. Tsai and Marek-Sadowska, M., Analysis of process variation's effect on SRAM's read stability, in Quality Electronic Design, 2006. ISQED '06. 7th International Symposium on, 2006, p. 8 pp. -610.
F. Makedon and Marek-Sadowska, M., Analysis of Heuristic Reasoning for the Visualization of CAD Quadratic, in ICCAL '89: Proceedings of the 2nd International Conference on Computer Assisted Learning, 1989, pp. 359–378.

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