Publications
“Cube diagram bundles: a new representation of strongly unspecified multiple-valued functions and relations”, in Multiple-Valued Logic, 1997. Proceedings., 1997 27th International Symposium on, 1997, pp. 287 -292.
, “Crosstalk reduction by transistor sizing”, in Design Automation Conference, 1999. Proceedings of the ASP-DAC '99. Asia and South Pacific, 1999, pp. 137 -140 vol.1.
, “Crosstalk noise in FPGAs”, in Design Automation Conference, 2003. Proceedings, 2003, pp. 944 - 949.
, “Crosstalk minimization for multiple clock tree routing”, in Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on, 2002, vol. 1, pp. I - 152-5 vol.1.
, “A crosstalk aware two-pin net router”, in Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on, 2003, vol. 5, p. V-485 - V-488 vol.5.
, “The crossing distribution problem”, in Computer-Aided Design, 1991. ICCAD-91. Digest of Technical Papers., 1991 IEEE International Conference on, 1991, pp. 528 -531.
, “Cost-free scan: a low-overhead scan path design methodology”, in Computer-Aided Design, 1995. ICCAD-95. Digest of Technical Papers., 1995 IEEE/ACM International Conference on, 1995, pp. 528 -533.
, “Coping with buffer delay change due to power and ground noise”, in Design Automation Conference, 2002. Proceedings. 39th, 2002, pp. 860 - 865.
, “A congestion-driven placement framework with local congestion prediction”, in GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI, 2005, pp. 488–493.
, “Congestion minimization during placement without estimation”, in Computer Aided Design, 2002. ICCAD 2002. IEEE/ACM International Conference on, 2002, pp. 739 - 745.
, “On computational complexity of a detailed routing problem in two dimensional FPGAs”, in VLSI, 1994. Design Automation of High Performance VLSI Systems. GLSV '94, Proceedings., Fourth Great Lakes Symposium on, 1994, pp. 70 -75.
, “Closed-form crosstalk noise metrics for physical design applications”, in Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings, 2002, pp. 812 - 819.
, “Clock skew optimization for ground bounce control”, in Computer-Aided Design, 1996. ICCAD-96. Digest of Technical Papers., 1996 IEEE/ACM International Conference on, 1996, pp. 395 -399.
, “Clock skew bounds estimation under power supply and process variations”, in GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI, 2005, pp. 332–336.
, “Clock network sizing via sequential linear programming with time-domain analysis”, in ISPD '04: Proceedings of the 2004 international symposium on Physical design, 2004, pp. 182–189.
, “Circuit partitioning with logic perturbation”, in Computer-Aided Design, 1995. ICCAD-95. Digest of Technical Papers., 1995 IEEE/ACM International Conference on, 1995, pp. 650 -655.
, “Circuit clustering using graph coloring”, in ISPD '99: Proceedings of the 1999 international symposium on Physical design, 1999, pp. 164–169.
, “Capturing input switching dependency in crosstalk noise modeling”, in ASIC/SOC Conference, 2000. Proceedings. 13th Annual IEEE International, 2000, pp. 330 -334.
, “Can pin access limit the footprint scaling?”, in Proceedings of the 49th Annual Design Automation Conference, 2012, pp. 1100–1106.
, “Buffer sizing for clock power minimization subject to general skew constraints”, in Design Automation Conference, 2004. Proceedings. 41st, 2004, pp. 159 -164.
, “Buffer minimization and time-multiplexed I/O on dynamically reconfigurable FPGAs”, in FPGA '97: Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays, 1997, pp. 142–148.
, “Boolean Matching Using Generalized Reed-Muller Forms”, in Design Automation, 1994. 31st Conference on, 1994, pp. 339 - 344.
, “Benefits and costs of power-gating technique”, in 2005 IEEE International Conference on Computer Design , 2005, pp. 559 - 566.
, “Automatic Sizing of Power/Ground (P/G) Networks in VLSI”, in Design Automation, 1989. 26th Conference on, 1989, pp. 783 - 786.
, “ATPG-based logic synthesis: an overview”, in Computer Aided Design, 2002. ICCAD 2002. IEEE/ACM International Conference on, 2002, pp. 786 - 789.
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