Publications

Found 231 results
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K. Wang and Marek-Sadowska, M., “On-chip power-supply network optimization using multigrid-based technique”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, pp. 407 - 417, 2005.
Z. Wang, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., “Diagnosis of hold time defects”, in Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. IEEE International Conference on, 2004, pp. 192 - 199.
K. Wang and Marek-Sadowska, M., “Clock network sizing via sequential linear programming with time-domain analysis”, in ISPD '04: Proceedings of the 2004 international symposium on Physical design, 2004, pp. 182–189.
S. - H. Weng, Kuo, Y. - M., Chang, S. - C., and Marek-Sadowska, M., “Timing analysis considering IR drop waveforms in power gating designs”, in Computer Design, 2008. ICCD 2008. IEEE International Conference on, 2008, pp. 532 -537.
Y. - L. Wu and Marek-Sadowska, M., “Efficient ordered binary decision diagrams minimization based on heuristics of cover pattern processing”, in Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on, 1993, pp. 273 -277.
Y. - L. Wu, Tsukiyama, S., and Marek-Sadowska, M., “On computational complexity of a detailed routing problem in two dimensional FPGAs”, in VLSI, 1994. Design Automation of High Performance VLSI Systems. GLSV '94, Proceedings., Fourth Great Lakes Symposium on, 1994, pp. 70 -75.
Y. - L. Wu and Marek-Sadowska, M., “Graph based analysis of FPGA routing”, in Design Automation Conference, 1993, with EURO-VHDL '93. Proceedings EURO-DAC '93. European, 1993, pp. 104 -109.
Y. - L. Wu and Marek-Sadowska, M., “Routing on regular segmented 2-D FPGAs”, in Design Automation Conference, 1995. Proceedings of the ASP-DAC '95/CHDL '95/VLSI '95., IFIP International Conference on Hardware Description Languages; IFIP International Conference on Very Large Scale Integration., Asian and South Pacific, 1995, pp. 329 -334.
Y. - L. Wu and Marek-Sadowska, M., “An efficient router for 2-D field programmable gate array”, in European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings., 1994, pp. 412 -416.
Y. - L. Wu, Tsukiyama, S., and Marek-Sadowska, M., “Graph based analysis of 2-D FPGA routing”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 15, pp. 33 -44, 1996.
Y. - L. Wu and Marek-Sadowska, M., “Routing for array-type FPGA's”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 16, pp. 506 -518, 1997.
Y. - L. Wu, Chang, D., Marek-Sadowska, M., and Tsukiyama, S., “Not necessarily more switches more routability [sic.]”, in Design Automation Conference 1997. Proceedings of the ASP-DAC '97. Asia and South Pacific, 1997, pp. 579 -584.
Y. - L. Wu and Marek-Sadowska, M., “Orthogonal Greedy Coupling - A New Optimization Approach to 2-D FPGA Routing”, in Design Automation, 1995. DAC '95. 32nd Conference on, 1995, pp. 568 -573.
Y. - L. Wu, Fan, H., Marek-Sadowska, M., and Wong, C. K., “OBDD minimization based on two-level representation of Boolean functions”, Computers, IEEE Transactions on, vol. 49, pp. 1371 -1379, 2000.
J. - Y. Wuu, Pikus, F. G., Marek-Sadowska, M., and Rieger, M. L., “Efficient approach to early detection of lithographic hotspots using machine learning systems and pattern matching”, in Design for Manufacturability through Design-Process Integration V, 2011, vol. 7974.
J. - Y. Wuu, Pikus, F. G., and Marek-Sadowska, M., “Metrics for characterizing machine learning-based hotspot detection methods”, in Quality Electronic Design (ISQED), 2011 12th International Symposium on, 2011, pp. 1 -6.
J. - Y. Wuu, Pikus, F. G., and Marek-Sadowska, M., “Fast and simple modeling of non-rectangular transistors”, in Society of Photo-Optical Instrumentation Engineers (SPIE) Conference Series, 2008, vol. 7122.
J. - Y. Wuu, Pikus, F. G., Torres, A., and Marek-Sadowska, M., “Rapid layout pattern classification”, in Design Automation Conference (ASP-DAC), 2011 16th Asia and South Pacific, 2011, pp. 781 -786.
J. - Y. Wuu, Pikus, F. G., Torres, A., Marek-Sadowska, M., Singh, V. K., and Rieger, M. L., “Detecting context sensitive hot spots in standard cell libraries”, in Design for Manufacturability through Design-Process Integration III, 2009, vol. 7275, p. 727515.
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T. Xiao and Marek-Sadowska, M., “Worst delay estimation in crosstalk aware static timing analysis”, in Computer Design, 2000. Proceedings. 2000 International Conference on, 2000, pp. 115 -120.
T. Xiao and Marek-Sadowska, M., “Efficient delay calculation in presence of crosstalk”, in Quality Electronic Design, 2000. ISQED 2000. Proceedings. IEEE 2000 First International Symposium on, 2000, pp. 491 -497.
T. Xiao and Marek-Sadowska, M., “Crosstalk reduction by transistor sizing”, in Design Automation Conference, 1999. Proceedings of the ASP-DAC '99. Asia and South Pacific, 1999, pp. 137 -140 vol.1.
T. Xiao and Marek-Sadowska, M., “Gate sizing to eliminate crosstalk induced timing violation”, in Computer Design, 2001. ICCD 2001. Proceedings. 2001 International Conference on, 2001, pp. 186 -191.
T. Xiao, Chang, C. - W., and Marek-Sadowska, M., “Efficient static timing analysis in presence of crosstalk”, in ASIC/SOC Conference, 2000. Proceedings. 13th Annual IEEE International, 2000, pp. 335 -339.
T. Xiao and Marek-Sadowska, M., “Functional correlation analysis in crosstalk induced critical paths identification”, in Design Automation Conference, 2001. Proceedings, 2001, pp. 653 - 656.

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