Publications

Found 231 results
2008
A. Todri and Marek-Sadowska, M., A study of reliability issues in clock distribution networks, in Computer Design, 2008. ICCD 2008. IEEE International Conference on, 2008, pp. 101 -106.
Yi-Wei Lin, Marek-Sadowska, M., Maly, W., Pfitzner, A., and Kasprowicz, D., Is there always performance overhead for regular fabric?, in Computer Design, 2008. ICCD 2008. IEEE International Conference on, 2008, pp. 557 -562.
S. - H. Weng, Kuo, Y. - M., Chang, S. - C., and Marek-Sadowska, M., Timing analysis considering IR drop waveforms in power gating designs, in Computer Design, 2008. ICCD 2008. IEEE International Conference on, 2008, pp. 532 -537.
V. Mehta, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., Timing-Aware Multiple-Delay-Fault Diagnosis, in Quality Electronic Design, 2008. ISQED 2008. 9th International Symposium on, 2008, pp. 246 -253.
2009
J. - Y. Wuu, Pikus, F. G., Torres, A., Marek-Sadowska, M., Singh, V. K., and Rieger, M. L., Detecting context sensitive hot spots in standard cell libraries, in Design for Manufacturability through Design-Process Integration III, 2009, vol. 7275, p. 727515.
A. Todri and Marek-Sadowska, M., Electromigration study of power-gated grids, in ISLPED '09: Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design, 2009, pp. 315–318.
Y. - M. Kuo, Chang, Y. - T., Chang, S. - C., and Marek-Sadowska, M., Spare Cells With Constant Insertion for Engineering Change, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 28, pp. 456 -460, 2009.
A. Todri, Marek-Sadowska, M., Maire, F., and Matheron, C., A study of decoupling capacitor effectiveness in power and ground grid networks, in Quality of Electronic Design, 2009. ISQED 2009. Quality Electronic Design, 2009, pp. 653 -658.
V. Mehta, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., Timing-Aware Multiple-Delay-Fault Diagnosis, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 28, pp. 245 -258, 2009.
Yi-Wei Lin, Marek-Sadowska, M., and Maly, W., Transistor-level layout of high-density regular circuits, in ISPD '09: Proceedings of the 2009 international symposium on Physical design, 2009, pp. 83–90.
2010
Yi-Wei Lin, Marek-Sadowska, M., and Maly, W., Layout Generator for Transistor-Level High-Density Regular Circuits, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 29, pp. 197 -210, 2010.
Li, Di-an, Marek-Sadowska, M., and Lee, B., On-chip em-sensitive interconnect structures, in SLIP '10: Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction, 2010, pp. 43–50.
Yi-Wei Lin, Marek-Sadowska, M., and Maly, W., Performance study of VeSFET-based, high-density regular circuits, in ISPD '10: Proceedings of the 19th international symposium on Physical design, 2010, pp. 161–168.
V. S. Nandakumar, Newmark, D., Zhan, Y., and Marek-Sadowska, M., Statistical static timing analysis flow for transistor level macros in a microprocessor, in Quality Electronic Design (ISQED), 2010 11th International Symposium on, 2010, pp. 163 -170.
2011
Yi-Wei Lin, Marek-Sadowska, M., and Maly, W., On Cell Layout-Performance Relationships in VeSFET-Based, High-Density Regular Circuits, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 30, pp. 229 -241, 2011.
J. - Y. Wuu, Pikus, F. G., Marek-Sadowska, M., and Rieger, M. L., Efficient approach to early detection of lithographic hotspots using machine learning systems and pattern matching, in Design for Manufacturability through Design-Process Integration V, 2011, vol. 7974.
V. S. Nandakumar and Marek-Sadowska, M., Layout effects in fine grain 3D integrated regular microprocessor blocks, in Design Automation Conference (DAC), 2011 48th ACM/EDAC/IEEE, 2011, pp. 639 -644.
V. S. Nandakumar and Marek-Sadowska, M., Low power, high throughput network-on-chip fabric for 3D multicore processors, in Computer Design (ICCD), 2011 IEEE 29th International Conference on, 2011, pp. 453 -454.
J. - Y. Wuu, Pikus, F. G., and Marek-Sadowska, M., Metrics for characterizing machine learning-based hotspot detection methods, in Quality Electronic Design (ISQED), 2011 12th International Symposium on, 2011, pp. 1 -6.
M. Marek-Sadowska, On old and new routing problems, in ISPD '11: Proceedings of the 2011 international symposium on Physical design, 2011, pp. 13–20.
Y. - S. Su, Wang, D. - C., Chang, S. - C., and Marek-Sadowska, M., Performance Optimization Using Variable-Latency Design Style, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 19, pp. 1874 -1883, 2011.
A. Todri and Marek-Sadowska, M., Power Delivery for Multicore Systems, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 19, pp. 2243 -2255, 2011.
J. - Y. Wuu, Pikus, F. G., Torres, A., and Marek-Sadowska, M., Rapid layout pattern classification, in Design Automation Conference (ASP-DAC), 2011 16th Asia and South Pacific, 2011, pp. 781 -786.
A. Todri and Marek-Sadowska, M., Reliability Analysis and Optimization of Power-Gated ICs, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 19, pp. 457 -468, 2011.
M. Marek-Sadowska and Qiu, X., A study on cell-level routing for VeSFET circuits, in Mixed Design of Integrated Circuits and Systems (MIXDES), 2011 Proceedings of the 18th International Conference, 2011, pp. 127 -132.

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