Publications

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S
B. Hu, Jiang, H., Liu, Q., and Marek-Sadowska, M., “Synthesis and placement flow for gain-based programmable regular fabrics”, in ISPD '03: Proceedings of the 2003 international symposium on Physical design, 2003, pp. 197–203.
P
H. Jiang and Marek-Sadowska, M., “Power/Ground Supply Network Optimization for Power-Gating”, in Computer Design, 2006. ICCD 2006. International Conference on, 2006, pp. 332 -337.
H. Jiang and Marek-Sadowska, M., “Power-Gating Aware Floorplanning”, in Quality Electronic Design, 2007. ISQED '07. 8th International Symposium on, 2007, pp. 853 -860.
H. Jiang and Marek-Sadowska, M., “Power gating scheduling for power/ground noise reduction”, in Design Automation Conference, 2008. DAC 2008. 45th ACM/IEEE, 2008, pp. 980 -985.
Y. - M. Jiang, Krstic, A., Cheng, K. - T., and Marek-Sadowska, M., “Post-layout Logic Restructuring For Performance Optimization”, in Design Automation Conference, 1997. Proceedings of the 34th, 1997, pp. 662 -665.
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K. Wang, Ran, Y., Jiang, H., and Marek-Sadowska, M., “General skew constrained clock network sizing based on sequential linear programming”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, pp. 773 - 782, 2005.
D
M. Perkowski, Marek-Sadowska, M., Jozwiak, L., Luba, T., Grygiel, S., Nowicka, M., Malvi, R., Wang, Z., and Zhang, J. S., “Decomposition of multiple-valued relations”, in Multiple-Valued Logic, 1997. Proceedings., 1997 27th International Symposium on, 1997, pp. 13 -18.
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S. Grygiel, Perkowski, M., Marek-Sadowska, M., Luba, T., and Jozwiak, L., “Cube diagram bundles: a new representation of strongly unspecified multiple-valued functions and relations”, in Multiple-Valued Logic, 1997. Proceedings., 1997 27th International Symposium on, 1997, pp. 287 -292.
H. Jiang, Wang, K., and Marek-Sadowska, M., “Clock skew bounds estimation under power supply and process variations”, in GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI, 2005, pp. 332–336.
B
H. Jiang, Marek-Sadowska, M., and Nassif, S. R., “Benefits and costs of power-gating technique”, in 2005 IEEE International Conference on Computer Design , 2005, pp. 559 - 566.