Publications

Found 7 results
Filters: First Letter Of Last Name is J and Author is Hailin Jiang  [Clear All Filters]
Journal Article
K. Wang, Ran, Y., Jiang, H., and Marek-Sadowska, M., General skew constrained clock network sizing based on sequential linear programming, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, pp. 773 - 782, 2005.
Conference Paper
B. Hu, Jiang, H., Liu, Q., and Marek-Sadowska, M., Synthesis and placement flow for gain-based programmable regular fabrics, in ISPD '03: Proceedings of the 2003 international symposium on Physical design, 2003, pp. 197–203.
H. Jiang and Marek-Sadowska, M., Power/Ground Supply Network Optimization for Power-Gating, in Computer Design, 2006. ICCD 2006. International Conference on, 2006, pp. 332 -337.
H. Jiang and Marek-Sadowska, M., Power-Gating Aware Floorplanning, in Quality Electronic Design, 2007. ISQED '07. 8th International Symposium on, 2007, pp. 853 -860.
H. Jiang and Marek-Sadowska, M., Power gating scheduling for power/ground noise reduction, in Design Automation Conference, 2008. DAC 2008. 45th ACM/IEEE, 2008, pp. 980 -985.
H. Jiang, Wang, K., and Marek-Sadowska, M., Clock skew bounds estimation under power supply and process variations, in GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI, 2005, pp. 332–336.
H. Jiang, Marek-Sadowska, M., and Nassif, S. R., Benefits and costs of power-gating technique, in 2005 IEEE International Conference on Computer Design , 2005, pp. 559 - 566.