Publications

Found 11 results
Filters: First Letter Of Last Name is W and Author is Yu-Liang Wu  [Clear All Filters]
Conference Paper
Y. - L. Wu, Tsukiyama, S., and Marek-Sadowska, M., On computational complexity of a detailed routing problem in two dimensional FPGAs, in VLSI, 1994. Design Automation of High Performance VLSI Systems. GLSV '94, Proceedings., Fourth Great Lakes Symposium on, 1994, pp. 70 -75.
Y. - L. Wu and Marek-Sadowska, M., Efficient ordered binary decision diagrams minimization based on heuristics of cover pattern processing, in Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on, 1993, pp. 273 -277.
Y. - L. Wu and Marek-Sadowska, M., An efficient router for 2-D field programmable gate array, in European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings., 1994, pp. 412 -416.
Y. - L. Wu and Marek-Sadowska, M., Graph based analysis of FPGA routing, in Design Automation Conference, 1993, with EURO-VHDL '93. Proceedings EURO-DAC '93. European, 1993, pp. 104 -109.
Y. - L. Wu, Chang, D., Marek-Sadowska, M., and Tsukiyama, S., Not necessarily more switches more routability [sic.], in Design Automation Conference 1997. Proceedings of the ASP-DAC '97. Asia and South Pacific, 1997, pp. 579 -584.
Y. - L. Wu and Marek-Sadowska, M., Orthogonal Greedy Coupling - A New Optimization Approach to 2-D FPGA Routing, in Design Automation, 1995. DAC '95. 32nd Conference on, 1995, pp. 568 -573.
Y. - L. Wu and Marek-Sadowska, M., Routing on regular segmented 2-D FPGAs, in Design Automation Conference, 1995. Proceedings of the ASP-DAC '95/CHDL '95/VLSI '95., IFIP International Conference on Hardware Description Languages; IFIP International Conference on Very Large Scale Integration., Asian and South Pacific, 1995, pp. 329 -334.
C. - C. Lin, Chang, D., Wu, Y. - L., and Marek-Sadowska, M., Time-multiplexed routing resources for FPGA design, in Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996, 1996, pp. 152 -155.
Journal Article
Y. - L. Wu, Tsukiyama, S., and Marek-Sadowska, M., Graph based analysis of 2-D FPGA routing, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 15, pp. 33 -44, 1996.
Y. - L. Wu, Fan, H., Marek-Sadowska, M., and Wong, C. K., OBDD minimization based on two-level representation of Boolean functions, Computers, IEEE Transactions on, vol. 49, pp. 1371 -1379, 2000.
Y. - L. Wu and Marek-Sadowska, M., Routing for array-type FPGA's, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 16, pp. 506 -518, 1997.