Publications

Found 11 results
Filters: First Letter Of Last Name is W and Author is Kai Wang  [Clear All Filters]
Conference Paper
K. Wang and Marek-Sadowska, M., Buffer sizing for clock power minimization subject to general skew constraints, in Design Automation Conference, 2004. Proceedings. 41st, 2004, pp. 159 -164.
K. Wang and Marek-Sadowska, M., Clock network sizing via sequential linear programming with time-domain analysis, in ISPD '04: Proceedings of the 2004 international symposium on Physical design, 2004, pp. 182–189.
H. Jiang, Wang, K., and Marek-Sadowska, M., Clock skew bounds estimation under power supply and process variations, in GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI, 2005, pp. 332–336.
C. - W. Chang, Wang, K., and Marek-Sadowska, M., Layout-driven hot-carrier degradation minimization using logic restructuring techniques, in Design Automation Conference, 2001. Proceedings, 2001, pp. 97 - 102.
K. Wang and Marek-Sadowska, M., On-chip power supply network optimization using multigrid-based technique, in Design Automation Conference, 2003. Proceedings, 2003, pp. 113 - 118.
K. Wang and Marek-Sadowska, M., Potential slack budgeting with clock skew optimization, in Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. IEEE International Conference on, 2004, pp. 265 - 271.
K. Wang and Marek-Sadowska, M., Power/ground mesh area optimization using multigrid-based technique [IC design], in Design, Automation and Test in Europe Conference and Exhibition, 2003, 2003, pp. 850 - 855.
A. Mukherjee, Wang, K., Chen, L. H., and Marek-Sadowska, M., Sizing power/ground meshes for clocking and computing circuit components, in Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings, 2002, pp. 176 -183.
Journal Article
C. - W. Chang, Hsiao, M. - F., Hu, B., Wang, K., Marek-Sadowska, M., Cheng, C. - K., and Chen, S. - J., Fast postplacement optimization using functional symmetries, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 23, pp. 102 - 118, 2004.
K. Wang, Ran, Y., Jiang, H., and Marek-Sadowska, M., General skew constrained clock network sizing based on sequential linear programming, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, pp. 773 - 782, 2005.
K. Wang and Marek-Sadowska, M., On-chip power-supply network optimization using multigrid-based technique, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, pp. 407 - 417, 2005.