Publications

Found 231 results
Filters: Filter is   [Clear All Filters]
2003
A. Singh, Mukherjee, A., Macchiarulo, L., and Marek-Sadowska, M., PITIA: an FPGA for throughput-intensive applications, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 11, pp. 354 -363, 2003.
K. Wang and Marek-Sadowska, M., Power/ground mesh area optimization using multigrid-based technique [IC design], in Design, Automation and Test in Europe Conference and Exhibition, 2003, 2003, pp. 850 - 855.
B. Hu, Jiang, H., Liu, Q., and Marek-Sadowska, M., Synthesis and placement flow for gain-based programmable regular fabrics, in ISPD '03: Proceedings of the 2003 international symposium on Physical design, 2003, pp. 197–203.
D. Chai, Kondratyev, A., Ran, Y., Tseng, K., Watanabe, Y., and Marek-Sadowska, M., Temporofunctional crosstalk noise analysis, in Design Automation Conference, 2003. Proceedings, 2003, pp. 860 - 863.
A. Mukherjee and Marek-Sadowska, M., Wave steering to integrate logic and physical syntheses, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 11, pp. 105 -120, 2003.
B. Hu and Marek-Sadowska, M., Wire length prediction based clustering and its application in placement, in Design Automation Conference, 2003. Proceedings, 2003, pp. 800 - 805.
Q. Liu, Hu, B., and Marek-Sadowska, M., Wire length prediction in constraint driven placement, in SLIP '03: Proceedings of the 2003 international workshop on System-level interconnect prediction, 2003, pp. 99–105.
2002
C. - W. Chang and Marek-Sadowska, M., ATPG-based logic synthesis: an overview, in Computer Aided Design, 2002. ICCAD 2002. IEEE/ACM International Conference on, 2002, pp. 786 - 789.
L. H. Chen and Marek-Sadowska, M., Closed-form crosstalk noise metrics for physical design applications, in Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings, 2002, pp. 812 - 819.
B. Hu and Marek-Sadowska, M., Congestion minimization during placement without estimation, in Computer Aided Design, 2002. ICCAD 2002. IEEE/ACM International Conference on, 2002, pp. 739 - 745.
L. H. Chen, Marek-Sadowska, M., and Brewer, F., Coping with buffer delay change due to power and ground noise, in Design Automation Conference, 2002. Proceedings. 39th, 2002, pp. 860 - 865.
M. - F. Hsiao, Marek-Sadowska, M., and Chen, S. - J., Crosstalk minimization for multiple clock tree routing, in Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on, 2002, vol. 1, pp. I - 152-5 vol.1.
A. Singh and Marek-Sadowska, M., Efficient circuit clustering for area and power reduction in FPGAs, in FPGA '02: Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays, 2002, pp. 59–66.
A. Singh, Parthasarathy, G., and Marek-Sadowska, M., Efficient circuit clustering for area and power reduction in FPGAs, ACM Trans. Des. Autom. Electron. Syst., vol. 7, pp. 643–663, 2002.
L. H. Chen and Marek-Sadowska, M., Efficient closed-form crosstalk delay metrics, in Quality Electronic Design, 2002. Proceedings. International Symposium on, 2002, pp. 431 - 436.
B. Hu and Marek-Sadowska, M., FAR: fixed-points addition & relaxation based placement, in ISPD '02: Proceedings of the 2002 international symposium on Physical design, 2002, pp. 161–166.
A. Singh and Marek-Sadowska, M., FPGA interconnect planning, in SLIP '02: Proceedings of the 2002 international workshop on System-level interconnect prediction, 2002, pp. 23–30.
L. H. Chen and Marek-Sadowska, M., Incremental delay change due to crosstalk noise, in ISPD '02: Proceedings of the 2002 international symposium on Physical design, 2002, pp. 120–125.
A. Mukherjee, Wang, K., Chen, L. H., and Marek-Sadowska, M., Sizing power/ground meshes for clocking and computing circuit components, in Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings, 2002, pp. 176 -183.
2001
L. H. Chen and Marek-Sadowska, M., Aggressor alignment for worst-case crosstalk noise, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 20, pp. 612 -621, 2001.
T. Xiao and Marek-Sadowska, M., Functional correlation analysis in crosstalk induced critical paths identification, in Design Automation Conference, 2001. Proceedings, 2001, pp. 653 - 656.
T. Xiao and Marek-Sadowska, M., Gate sizing to eliminate crosstalk induced timing violation, in Computer Design, 2001. ICCD 2001. Proceedings. 2001 International Conference on, 2001, pp. 186 -191.
N. Funabiki, Singh, A., Mukherjee, A., and Marek-Sadowska, M., A global routing technique for wave-steered design methodology, in Digital Systems, Design, 2001. Proceedings. Euromicro Symposium on, 2001, pp. 430 -436.
C. - W. Chang, Hu, B., and Marek-Sadowska, M., In-place delay constrained power optimization using functional symmetries, in Design, Automation and Test in Europe, 2001. Conference and Exhibition 2001. Proceedings, 2001, pp. 377 -382.
G. Parthasarathy, Marek-Sadowska, M., Mukherjee, A., and Singh, A., Interconnect complexity-aware FPGA placement using Rent's rule, in SLIP '01: Proceedings of the 2001 international workshop on System-level interconnect prediction, 2001, pp. 115–121.

Pages