| Title | Minimum-area sequential budgeting for FPGA |
| Publication Type | Conference Paper |
| Year of Publication | 2003 |
| Authors | Yeh, C-Y, Marek-Sadowska, M |
| Conference Name | Computer Aided Design, 2003. ICCAD-2003. International Conference on |
| Date Published | nov. |
| Keywords | C-SBGT algorithm, circuit optimisation, combinational circuits, delay budgeting, delay upper bounds, field programmable gate arrays, flipflop minimization, FPGA, minimum area sequential budgeting, optimization, sequential circuits, timing driven placement |
| Abstract | The constraint-based approach to timing-driven placement requires delay budgeting to define the delay upper bounds for nets. While most of the previous delay-budgeting works have been focused on optimizing combinational circuits, the work in introduces sequential budgeting, which combines budgeting and retiming to optimize sequential circuits better. However, the formulation does not consider flip-flop (FF) minimization, which is important in practical applications. Here, we propose a new sequential budgeting algorithm, C-SBGT, that not only controls the FF count, but also can be solved more efficiently compared. Our formulation has fewer constraints than and the procedure to realize retiming is also simpler. Our experiments show that our new min-area sequential budgeting algorithm produces a good trade-off between the area and budgeting optimization goals, as well as improving the timing of previous sequential budgeting method by 12%. |
| DOI | 10.1109/ICCAD.2003.1257902 |
