On Cell Layout-Performance Relationships in VeSFET-Based, High-Density Regular Circuits

TitleOn Cell Layout-Performance Relationships in VeSFET-Based, High-Density Regular Circuits
Publication TypeJournal Article
Year of Publication2011
AuthorsYi-Wei Lin, Marek-Sadowska, M, Maly, W
JournalComputer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Pagination229 -241
Date Publishedfeb.
Keywordscell interconnect layouts, cell layout-performance relationships, cell-level interconnect pattern, circuit layout, field effect transistors, high-density regular circuits, intracell routing, linear programming, linear programming-based technique, network routing, parallel metal tracks, super-regular transistor arrangement, vertical slit field effect transistors, VeSFET
AbstractIn this paper, we study circuits implemented using high-density arrays composed of vertical slit field effect transistors. This layout style could dramatically increase transistor density and, therefore, reduce fabrication cost. However, its geometrical restrictions, imposed by the super-regular transistor arrangement and strictly parallel metal tracks, pose new design challenges. Our experiments reveal that very dense cell-level interconnect pattern may be responsible for unnecessary 15% increase of the circuit level, critical path delays. We demonstrate that these extra delays can be avoided by constructing appropriate cell interconnect layouts and by more flexible usage of available metal layers for intra-cell routing. To balance the performance and metal layer usage, we propose a linear programming-based technique for critical net re-routing.