| Title | Test-point insertion: scan paths through functional logic |
| Publication Type | Journal Article |
| Year of Publication | 1998 |
| Authors | Lin, C-C, Marek-Sadowska, M, Cheng, K-T, Lee, T-C |
| Journal | Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on |
| Volume | 17 |
| Pagination | 838 -851 |
| Date Published | sep |
| ISSN | 0278-0070 |
| Keywords | design for testability, flip-flop, flip-flops, full-scan design, functional logic, logic design, logic testing, multiplexer, partial-scan design, scan path, test point insertion |
| Abstract | Conventional scan design imposes considerable area and delay overheads. To establish a scan chain in the test mode, multiplexers at the inputs of flip-flops and scan wires are added to the actual design. We propose a low-overhead scan design methodology that employs a new test-point insertion technique. Unlike the conventional test-point insertion, where test points are used directly to increase the controllability and observability of the selected signals, the test points are used here to establish scan paths through the functional logic. The proposed technique reuses the functional logic for scan operations; as a result, the design-for-testability overhead on area or timing can be minimized. We show an algorithm that uses the new test-point insertion technique to reduce the area overhead for the full-scan design. We also discuss its application to the timing-driven partial-scan design |
| DOI | 10.1109/43.720319 |
