| Title | Performance Optimization Using Variable-Latency Design Style |
| Publication Type | Journal Article |
| Year of Publication | 2011 |
| Authors | Su, Y-S, Wang, D-C, Chang, S-C, Marek-Sadowska, M |
| Journal | Very Large Scale Integration (VLSI) Systems, IEEE Transactions on |
| Volume | 19 |
| Pagination | 1874 -1883 |
| Date Published | oct. |
| ISSN | 1063-8210 |
| Keywords | heuristic methodology, hold logic, logic design, optimisation, performance optimization, short path activation condition, telescopic unit, timing constraint, variable-latency design style |
| Abstract | In many designs, the worst-case delay of a critical path may be activated infrequently. Traditional optimization approaches assume the worst-case conditions, which could lead to an inefficient resource usage. It is possible to improve the throughput of such designs by introducing variable latency. One existing realization of the variable-latency design style is based on telescopic units. The design of the hold logic in telescopic units influences the circuit's throughput. In this paper, we show that the traditionally designed hold logic may be inaccurate. We use the short path activation conditions to obtain more accurate hold logic and improve the efficiency of telescopic units. To reduce the overhead for large circuits, we propose an efficient heuristic methodology of constructing non-exact hold logic. We also discuss how to choose the telescopic unit's timing constraint. On average, our approach achieves the performance gain of 21.67% compared to 13.99%, reported in the previous work. |
| DOI | 10.1109/TVLSI.2010.2058874 |
