Publications

Found 3 results
Filters: Author is Chao-Yang Yeh and Keyword is sequential circuits  [Clear All Filters]
2004
C. - Y. Yeh and Marek-Sadowska, M., “Sequential delay budgeting with interconnect prediction”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 12, pp. 1028 -1037, 2004.
2003
C. - Y. Yeh and Marek-Sadowska, M., “Delay budgeting in sequential circuit with application on FPGA placement”, in Design Automation Conference, 2003. Proceedings, 2003, pp. 202 - 207.
C. - Y. Yeh and Marek-Sadowska, M., “Minimum-area sequential budgeting for FPGA”, in Computer Aided Design, 2003. ICCAD-2003. International Conference on, 2003, pp. 813 - 817.