- Vertical Slit Field Effect Transistor in ultra-low power applications
- Can pin access limit the footprint scaling?
- A Low Energy Network-on-Chip Fabric for 3-D Multi-Core Architectures
- Investigation of emerging middle-of-line poly gate-to-diffusion contact reliability issues
- Metrics for characterizing machine learning-based hotspot detection methods
- A study on cell-level routing for VeSFET circuits
- On Cell Layout-Performance Relationships in VeSFET-Based, High-Density Regular Circuits
Contact
Prof. Malgorzata Marek-Sadowska
Office Room 4111, Harold Frank Hall
Department of Electrical and Computer Engineering
University of California, Santa Barbara CA 93106.
Ph: (805) 893 2721
email: mms@ece.ucsb.edu
VLSI CAD LAB
Room 4108, Harold Frank Hall
Department of Electrical and Computer Engineering
University of California, Santa Barbara CA 93106.
Ph: (805) 893 5678
