- A Low Energy Network-on-Chip Fabric for 3-D Multi-Core Architectures
- Investigation of emerging middle-of-line poly gate-to-diffusion contact reliability issues
- Vertical Slit Field Effect Transistor in ultra-low power applications
- Can pin access limit the footprint scaling?
- On Cell Layout-Performance Relationships in VeSFET-Based, High-Density Regular Circuits
- Performance Optimization Using Variable-Latency Design Style
- Twin gate, vertical slit FET (VeSFET) for highly periodic layout and 3D integration
Vertical Slit Field Effect Transistor in ultra-low power applications
| Title | Vertical Slit Field Effect Transistor in ultra-low power applications |
| Publication Type | Conference Paper |
| Year of Publication | 2012 |
| Authors | Qiu, X, Marek-Sadowska, M, Maly, W |
| Conference Name | Quality Electronic Design (ISQED), 2012 13th International Symposium on |
| Date Published | march |
| DOI | 10.1109/ISQED.2012.6187522 |
