| Title | A study on cell-level routing for VeSFET circuits |
| Publication Type | Conference Paper |
| Year of Publication | 2011 |
| Authors | Marek-Sadowska, M, Qiu, X |
| Conference Name | Mixed Design of Integrated Circuits and Systems (MIXDES), 2011 Proceedings of the 18th International Conference |
| Date Published | june |
| Keywords | cell level routing, field effect integrated circuits, integrated circuit design, intercell routing, intercell white space, logic circuits, network routing, VeSFET circuits |
| Abstract | In this paper, we study the inter-cell routing of circuits implemented with VeSFET transistors. VeSFET-based cells have footprint significantly smaller than their CMOS counterparts and their layouts affect the inter-cell routability. We observe that cell footprint scaling leads to wire lengths reduction only when a sufficient number of inter-cell metal layers is available. Otherwise, the inter-cell white space needed for routing obliterates the potential benefits of footprint scaling. VeSFET-based circuits may benefit from routing on both sides of the transistor layer. |
