Skip to main content
Home
VLSI CAD LAB
University of California, Santa Barbara
  • Home
  • People
  • Research
  • Publications
  • Contact

Recent Papers

  • Vertical Slit Field Effect Transistor in ultra-low power applications
  • Can pin access limit the footprint scaling?
  • A Low Energy Network-on-Chip Fabric for 3-D Multi-Core Architectures
  • Investigation of emerging middle-of-line poly gate-to-diffusion contact reliability issues
  • Metrics for characterizing machine learning-based hotspot detection methods
  • A study on cell-level routing for VeSFET circuits
  • On Cell Layout-Performance Relationships in VeSFET-Based, High-Density Regular Circuits
More...

A Low Energy Network-on-Chip Fabric for 3-D Multi-Core Architectures

TitleA Low Energy Network-on-Chip Fabric for 3-D Multi-Core Architectures
Publication TypeJournal Article
Year of Publication2012
AuthorsNandakumar, VS, Marek-Sadowska, M
JournalEmerging and Selected Topics in Circuits and Systems, IEEE Journal on
Volume2
Pagination266 -277
Date Publishedjune
ISSN2156-3357
Keywords3D hybrid architecture, 3D multicore architectures, complementary metal-oxide-semiconductor-based homogeneous 3D NoC, energy consumption, field effect transistors, latency, low energy network-on-chip fabric, multiprocessing systems, network-on-chip, NoC, power aware computing, power saving techniques, vertical slit field effect transistors, VeSFET circuits
DOI10.1109/JETCAS.2012.2193834
  • Google Scholar
Electrical and Computer Engineering, Harold Frank Hall, University of California, Santa Barbara, CA - 93106.

Log In