Publications

Found 6 results
Filters: Keyword is logic CAD and Author is Yu-Liang Wu  [Clear All Filters]
1996
Y. - L. Wu, Tsukiyama, S., and Marek-Sadowska, M., Graph based analysis of 2-D FPGA routing, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 15, pp. 33 -44, 1996.
C. - C. Lin, Chang, D., Wu, Y. - L., and Marek-Sadowska, M., Time-multiplexed routing resources for FPGA design, in Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996, 1996, pp. 152 -155.
1995
Y. - L. Wu and Marek-Sadowska, M., Routing on regular segmented 2-D FPGAs, in Design Automation Conference, 1995. Proceedings of the ASP-DAC '95/CHDL '95/VLSI '95., IFIP International Conference on Hardware Description Languages; IFIP International Conference on Very Large Scale Integration., Asian and South Pacific, 1995, pp. 329 -334.
1994
Y. - L. Wu, Tsukiyama, S., and Marek-Sadowska, M., On computational complexity of a detailed routing problem in two dimensional FPGAs, in VLSI, 1994. Design Automation of High Performance VLSI Systems. GLSV '94, Proceedings., Fourth Great Lakes Symposium on, 1994, pp. 70 -75.
Y. - L. Wu and Marek-Sadowska, M., An efficient router for 2-D field programmable gate array, in European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings., 1994, pp. 412 -416.
1993
Y. - L. Wu and Marek-Sadowska, M., Graph based analysis of FPGA routing, in Design Automation Conference, 1993, with EURO-VHDL '93. Proceedings EURO-DAC '93. European, 1993, pp. 104 -109.