Time-multiplexed routing resources for FPGA design

TitleTime-multiplexed routing resources for FPGA design
Publication TypeConference Paper
Year of Publication1996
AuthorsLin, C-C, Chang, D, Wu, Y-L, Marek-Sadowska, M
Conference NameCustom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996
Date Publishedmay
Keywordschannel density, circuit layout CAD, circuit optimisation, circuit sizes, field programmable gate arrays, FPGA design, integrated circuit layout, logic CAD, look-up tables, network routing, permutation equivalent LUTs, programmable SRAMs, random-access storage, SRAM based FPGAs, table lookup, time division multiplexing, time phases, time-multiplexed routing resources, Xilinx 4000 style architecture
AbstractWe propose a time-multiplexed routing architecture for SRAM based FPGAs. This can be implemented by having two programmable SRAMs for each routing connection. The goal of this approach is to alleviate the on-chip routing bottleneck, and to increase the range of circuit sizes which can be accommodated on a single chip. We consider a Xilinx 4000 style architecture with and without time-multiplexed routing. Our experimental results show that time-multiplexed routing can reduce the channel density by 30%. Also, sharing permutation equivalent LUTs between the time phases can result in a 14% reduction of the number of LUTs required to implement a design