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Y. Ran and Marek-Sadowska, M., Via-Configurable Routing Architectures and Fast Design Mappability Estimation for Regular Fabrics, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 14, pp. 998 -1009, 2006.
Y. Ran and Marek-Sadowska, M., Designing a via-configurable regular fabric, in Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004, 2004, pp. 423 - 426.