| Title | Via-Configurable Routing Architectures and Fast Design Mappability Estimation for Regular Fabrics |
| Publication Type | Journal Article |
| Year of Publication | 2006 |
| Authors | Ran, Y, Marek-Sadowska, M |
| Journal | Very Large Scale Integration (VLSI) Systems, IEEE Transactions on |
| Volume | 14 |
| Pagination | 998 -1009 |
| Date Published | sept. |
| ISSN | 1063-8210 |
| Keywords | application specific integrated circuits, application-specified integrated circuits, ASICs, fast design mappability estimation, incremental cell movement scheme, integrated circuit design, integrated circuit interconnections, mappability, mask cost, network routing, regular fabrics, routability problem, via-configurable routing architectures, white-space allocation |
| Abstract | In this paper, we describe a new via-configurable routing architecture which shows a much better throughput and performance than the previous structures. We demonstrate how to construct a single-via-mask fabric to reduce the mask cost further, and we analyze the penalties which it incurs. To solve the routability problem commonly existing in fabric-based designs, an efficient white-space allocation and an incremental cell movement scheme are suggested, which help to provide a fast design convergence and early prediction of circuit's mappability to a given fabric |
| DOI | 10.1109/TVLSI.2006.884051 |
