Publications
Found 2 results
Filters: Keyword is logic testing and Author is Chien-Chung Tsai [Clear All Filters]
“Logic synthesis for testability”, in VLSI, 1996. Proceedings., Sixth Great Lakes Symposium on, 1996, pp. 118 -121.
, “Generalized Reed-Muller forms as a tool to detect symmetries”, Computers, IEEE Transactions on, vol. 45, pp. 33 -40, 1996.
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