Logic synthesis for testability

TitleLogic synthesis for testability
Publication TypeConference Paper
Year of Publication1996
AuthorsTsai, C-C, Marek-Sadowska, M
Conference NameVLSI, 1996. Proceedings., Sixth Great Lakes Symposium on
Date Publishedmar
Keywordsalgebraic factorization, AND gates, circuit design, design for testability, Fixed Polarity Reed-Muller form, logic design, logic testing, multilevel logic synthesis, multivalued logic circuits, OR gates, redundancy, single stuck-at fault testability
AbstractThis paper presents a multilevel logic synthesis method that achieves 100% single stuck-at fault testability. We assume any cell library composed of AND/OR gates. The Fixed Polarity Reed-Muller forms are used to build the initial design. Algebraic factorizations and redundancy removal are two major steps that are used in deriving the final circuit. A predetermined set of input patterns is applied to identify redundancies and serves as the test set for the resulting circuit. Therefore, test pattern generation is not needed. Experimental results show that our method produces circuits with area comparable to Berkeley SIS 1.2