| Title | Logic synthesis for testability |
| Publication Type | Conference Paper |
| Year of Publication | 1996 |
| Authors | Tsai, C-C, Marek-Sadowska, M |
| Conference Name | VLSI, 1996. Proceedings., Sixth Great Lakes Symposium on |
| Date Published | mar |
| Keywords | algebraic factorization, AND gates, circuit design, design for testability, Fixed Polarity Reed-Muller form, logic design, logic testing, multilevel logic synthesis, multivalued logic circuits, OR gates, redundancy, single stuck-at fault testability |
| Abstract | This paper presents a multilevel logic synthesis method that achieves 100% single stuck-at fault testability. We assume any cell library composed of AND/OR gates. The Fixed Polarity Reed-Muller forms are used to build the initial design. Algebraic factorizations and redundancy removal are two major steps that are used in deriving the final circuit. A predetermined set of input patterns is applied to identify redundancies and serves as the test set for the resulting circuit. Therefore, test pattern generation is not needed. Experimental results show that our method produces circuits with area comparable to Berkeley SIS 1.2 |
| DOI | 10.1109/GLSV.1996.497605 |
