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C
T. Xiao and Marek-Sadowska, M., “Crosstalk reduction by transistor sizing”, in Design Automation Conference, 1999. Proceedings of the ASP-DAC '99. Asia and South Pacific, 1999, pp. 137 -140 vol.1.
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K. Wang, Ran, Y., Jiang, H., and Marek-Sadowska, M., “General skew constrained clock network sizing based on sequential linear programming”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, pp. 773 - 782, 2005.