| Title | General skew constrained clock network sizing based on sequential linear programming |
| Publication Type | Journal Article |
| Year of Publication | 2005 |
| Authors | Wang, K, Ran, Y, Jiang, H, Marek-Sadowska, M |
| Journal | Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on |
| Volume | 24 |
| Pagination | 773 - 782 |
| Date Published | may |
| ISSN | 0278-0070 |
| Keywords | buffer width, circuit noise, circuit optimisation, clock network optimization, clock network sizing, clock path delay, clock skew, clocks, delays, divide and conquer methods, divide-and-conquer, first-order Taylor expansion, general skew constraints, linear programming, nonlinear programming problem, power supply circuits, power supply noise, process variation, sequential linear programming, time-domain analysis, wire width |
| Abstract | We investigate the problem of clock network sizing subject to general skew constraints. A novel approach based on sequential linear programming is presented. The original nonlinear programming problem is transformed into a sequence of linear programs by taking the first-order Taylor's expansion of clock path delay with respect to buffer and/or wire widths. For each linear program, the sensitivities of clock path delay, with respect to buffer and/or wire widths, are efficiently updated by applying time-domain analysis to the clock network in a divide-and-conquer fashion. Our technique can take into account power supply and process variations. We demonstrate experimentally that the proposed technique is not only capable of optimizing effectively the skew and area of clock network, but also of providing more accurate delay and skew results compared to the traditional approaches. |
| DOI | 10.1109/TCAD.2005.846362 |
