Found 2 results
Filters: Keyword is buffer circuits  [Clear All Filters]
Conference Paper
L. H. Chen, Marek-Sadowska, M., and Brewer, F., Coping with buffer delay change due to power and ground noise, in Design Automation Conference, 2002. Proceedings. 39th, 2002, pp. 860 - 865.
Journal Article
A. Vittal and Marek-Sadowska, M., Low-power buffered clock tree design, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 16, pp. 965 -975, 1997.