Coping with buffer delay change due to power and ground noise

TitleCoping with buffer delay change due to power and ground noise
Publication TypeConference Paper
Year of Publication2002
AuthorsChen, LH, Marek-Sadowska, M, Brewer, F
Conference NameDesign Automation Conference, 2002. Proceedings. 39th
Keywordsbuffer circuits, buffer delay model, carrier velocity saturation, delays, ground noise, integrated circuit modelling, integrated circuit noise, level-induced jitter, power noise, repeater chain, short-channel MOSFET, signal propagation, timing jitter, VLSI, VLSI circuit
AbstractVariation of power and ground levels affect VLSI circuit performance. Trends in device technology and in packaging have necessitated a revision in conventional delay models. In particular, simple scalable models are needed to predict delays in the presence of uncorrelated power and ground noise. In this paper, we analyze the effect of such noise on signal propagation through a buffer and present simple, closed-form formulas to estimate the corresponding change of delay. The model captures both positive (slowdown) and negative (speedup) delay changes. It is consistent with short-channel MOSFET behavior, including carrier velocity saturation effects. An application shows that repeater chains using buffers instead of inherently faster inverters tend to have superior supply level-induced jitter characteristics.