Publications

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Search results for Jiang H
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2005
H. Jiang, Wang, K., and Marek-Sadowska, M., “Clock skew bounds estimation under power supply and process variations”, in GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI, 2005, pp. 332–336.
K. Wang, Ran, Y., Jiang, H., and Marek-Sadowska, M., “General skew constrained clock network sizing based on sequential linear programming”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, pp. 773 - 782, 2005.