Publications

Found 6 results
Filters: Author is Bo Hu and Keyword is integrated circuit layout  [Clear All Filters]
2005
B. Hu and Marek-Sadowska, M., Multilevel fixed-point-addition-based VLSI placement, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, pp. 1188 - 1203, 2005.
2004
C. - W. Chang, Hsiao, M. - F., Hu, B., Wang, K., Marek-Sadowska, M., Cheng, C. - K., and Chen, S. - J., Fast postplacement optimization using functional symmetries, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 23, pp. 102 - 118, 2004.
B. Hu and Marek-Sadowska, M., Fine granularity clustering-based placement, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 23, pp. 527 - 536, 2004.
B. Hu and Marek-Sadowska, M., Multilevel expansion-based VLSI placement with blockages, in Computer Aided Design, 2004. ICCAD-2004. IEEE/ACM International Conference on, 2004, pp. 558-564.
2003
B. Hu and Marek-Sadowska, M., Wire length prediction based clustering and its application in placement, in Design Automation Conference, 2003. Proceedings, 2003, pp. 800 - 805.
2002
B. Hu and Marek-Sadowska, M., Congestion minimization during placement without estimation, in Computer Aided Design, 2002. ICCAD 2002. IEEE/ACM International Conference on, 2002, pp. 739 - 745.