Multilevel expansion-based VLSI placement with blockages

TitleMultilevel expansion-based VLSI placement with blockages
Publication TypeConference Paper
Year of Publication2004
AuthorsHu, B, Marek-Sadowska, M
Conference NameComputer Aided Design, 2004. ICCAD-2004. IEEE/ACM International Conference on
Date PublishedNov.
Keywordsexpansion-based placer, fixed point arithmetic, fixed-point addition, integrated circuit layout, intellectual property blocks, multilevel expansion-based VLSI placement, quadratic placement technique, standard-cell placement problem, system-on-chip, system-on-chip design, VLSI
AbstractThe rapid growth of system-on-chip designs makes it a necessity for physical design tools to efficiently handle the coexistence of large intellectual property (IP) blocks and small standard cells in a single design. In this work, we present an efficient expansion-based placer to address standard-cell placement problem in the presence of blockages induced by pre-placed IP blocks. Expansion refers to the process during which cells are gradually distributed over a specified region. We implement expansion in a new placer by enhancing a quadratic placement technique based on fixed-point addition originally presented by B. Hu and M. Marek-Sadowska (2003), where fixed points were defined as dimensionless pseudo cells, and were deliberately introduced into the circuit to pull cells from one location to another. The new placer not only produces very competitive placement results over multiple sets of public-domain benchmarks with conventional rectangle-like chip boundary, but also efficiently handles the existence of blockages. Especially, we develop three expansion strategies and use them under different blockage settings.