Fast postplacement optimization using functional symmetries

TitleFast postplacement optimization using functional symmetries
Publication TypeJournal Article
Year of Publication2004
AuthorsChang, C-W, Hsiao, M-F, Hu, B, Wang, K, Marek-Sadowska, M, Cheng, C-K, Chen, S-J
JournalComputer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Pagination102 - 118
Date Publishedjan
KeywordsBoolean functions, Boolean network functional symmetries, circuit optimisation, delay optimization, fast postplacement optimization, functional symmetry, gate-sizing algorithm, integrated circuit layout, integrated circuit reliability, linear-time algorithm, logic design, logic restructuring, logic synthesis, physical design, power optimization, reliability optimization, rewiring, rewiring engine, symmetry, timing, timing closure
AbstractThe timing-convergence problem arises because estimations made during logic synthesis may not be met during physical design. In this paper, an efficient rewiring engine is proposed to explore maximal freedom after placement. The most important feature of this approach is that the existing placement solution is left intact throughout the optimization. A linear-time algorithm is proposed to detect functional symmetries in the Boolean network which are then used as the basis for rewiring. Integration with an existing gate-sizing algorithm further proves the effectiveness of our technique. Three applications are demonstrated: delay, power, and reliability optimization.