Publications

Found 4 results
Filters: Keyword is circuit optimisation and Author is Bo Hu  [Clear All Filters]
2001
C. - W. Chang, Hu, B., and Marek-Sadowska, M., “In-place delay constrained power optimization using functional symmetries”, in Design, Automation and Test in Europe, 2001. Conference and Exhibition 2001. Proceedings, 2001, pp. 377 -382.
2002
B. Hu and Marek-Sadowska, M., “Congestion minimization during placement without estimation”, in Computer Aided Design, 2002. ICCAD 2002. IEEE/ACM International Conference on, 2002, pp. 739 - 745.
2004
C. - W. Chang, Hsiao, M. - F., Hu, B., Wang, K., Marek-Sadowska, M., Cheng, C. - K., and Chen, S. - J., “Fast postplacement optimization using functional symmetries”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 23, pp. 102 - 118, 2004.
B. Hu and Marek-Sadowska, M., “Fine granularity clustering-based placement”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 23, pp. 527 - 536, 2004.