In-place delay constrained power optimization using functional symmetries

TitleIn-place delay constrained power optimization using functional symmetries
Publication TypeConference Paper
Year of Publication2001
AuthorsChang, C-W, Hu, B, Marek-Sadowska, M
Conference NameDesign, Automation and Test in Europe, 2001. Conference and Exhibition 2001. Proceedings
Keywordsbuffer insertion, circuit CAD, circuit optimisation, CMOS logic circuits, delay constrained power optimization, delays, functional symmetries, functional symmetry based rewiring, gate sizing, in-place optimization, integrated circuit design, logic CAD, logic synthesis, low-power electronics, power estimation, power reduction, transition density
AbstractIn-Place Optimization (IPO) has become the backend methodology of choice to resolve the gap between logic synthesis and physical design as the optimization can be guided by accurate physical information. To perform optimization without perturbing too much the placed netlist, only buffer insertion and gate sizing are commonly used in current design tools. In this paper, we address the problem of delay-constrained power optimization by introducing another degree of freedom: functional symmetry based rewiring. Theoretical results on the effect of using functional symmetry on transition density for power estimation is also derived. Experimental results show that, under the same delay constraint, our technique achieves much better power reduction as compared to the discrete gate sizing only technique