Publications

Found 2 results
Filters: Keyword is VeSFET circuits  [Clear All Filters]
2012
V. S. Nandakumar and Marek-Sadowska, M., A Low Energy Network-on-Chip Fabric for 3-D Multi-Core Architectures, Emerging and Selected Topics in Circuits and Systems, IEEE Journal on, vol. 2, pp. 266 -277, 2012.
2011
M. Marek-Sadowska and Qiu, X., A study on cell-level routing for VeSFET circuits, in Mixed Design of Integrated Circuits and Systems (MIXDES), 2011 Proceedings of the 18th International Conference, 2011, pp. 127 -132.